1;/*************************************************************************** 2; * Copyright (c) 2024 Microsoft Corporation 3; * 4; * This program and the accompanying materials are made available under the 5; * terms of the MIT License which is available at 6; * https://opensource.org/licenses/MIT. 7; * 8; * SPDX-License-Identifier: MIT 9; **************************************************************************/ 10; 11; 12;/**************************************************************************/ 13;/**************************************************************************/ 14;/** */ 15;/** ThreadX Component */ 16;/** */ 17;/** Thread */ 18;/** */ 19;/**************************************************************************/ 20;/**************************************************************************/ 21; 22; 23;#define TX_SOURCE_CODE 24; 25; 26;/* Include necessary system files. */ 27; 28;#include "tx_api.h" 29;#include "tx_thread.h" 30; 31; 32FIQ_DISABLE EQU 0x40 ; FIQ disable bit 33MODE_MASK EQU 0x1F ; Mode mask 34SYS_MODE_BITS EQU 0x1F ; System mode bits 35; 36; 37 AREA ||.text||, CODE, READONLY 38;/**************************************************************************/ 39;/* */ 40;/* FUNCTION RELEASE */ 41;/* */ 42;/* _tx_thread_fiq_nesting_start ARM11/AC5 */ 43;/* 6.1 */ 44;/* AUTHOR */ 45;/* */ 46;/* William E. Lamie, Microsoft Corporation */ 47;/* */ 48;/* DESCRIPTION */ 49;/* */ 50;/* This function is called by the application from FIQ mode after */ 51;/* _tx_thread_fiq_context_save has been called and switches the FIQ */ 52;/* processing to the system mode so nested FIQ interrupt processing */ 53;/* is possible (system mode has its own "lr" register). Note that */ 54;/* this function assumes that the system mode stack pointer was setup */ 55;/* during low-level initialization (tx_initialize_low_level.s). */ 56;/* */ 57;/* This function returns with FIQ interrupts enabled. */ 58;/* */ 59;/* INPUT */ 60;/* */ 61;/* None */ 62;/* */ 63;/* OUTPUT */ 64;/* */ 65;/* None */ 66;/* */ 67;/* CALLS */ 68;/* */ 69;/* None */ 70;/* */ 71;/* CALLED BY */ 72;/* */ 73;/* ISRs */ 74;/* */ 75;/* RELEASE HISTORY */ 76;/* */ 77;/* DATE NAME DESCRIPTION */ 78;/* */ 79;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 80;/* */ 81;/**************************************************************************/ 82;VOID _tx_thread_fiq_nesting_start(VOID) 83;{ 84 EXPORT _tx_thread_fiq_nesting_start 85_tx_thread_fiq_nesting_start 86 MOV r3,lr ; Save ISR return address 87 MRS r0, CPSR ; Pickup the CPSR 88 BIC r0, r0, #MODE_MASK ; Clear the mode bits 89 ORR r0, r0, #SYS_MODE_BITS ; Build system mode CPSR 90 MSR CPSR_cxsf, r0 ; Enter system mode 91 STMDB sp!, {r1, lr} ; Push the system mode lr on the system mode stack 92 ; and push r1 just to keep 8-byte alignment 93 BIC r0, r0, #FIQ_DISABLE ; Build enable FIQ CPSR 94 MSR CPSR_cxsf, r0 ; Enter system mode 95 IF {INTER} = {TRUE} 96 BX r3 ; Return to caller 97 ELSE 98 MOV pc, r3 ; Return to caller 99 ENDIF 100;} 101; 102 END 103 104