1 /**************************************************************************/
2 /*                                                                        */
3 /*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4 /*                                                                        */
5 /*       This software is licensed under the Microsoft Software License   */
6 /*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7 /*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8 /*       and in the root directory of this software.                      */
9 /*                                                                        */
10 /**************************************************************************/
11 
12 #ifndef TM_PORTING_LAYER_H
13 #define TM_PORTING_LAYER_H
14 
15 #include <stdio.h>
16 
17 
18 /* Define the TRAP instruction. This is used by the Interrupt Processing and Interrupt Preemption Processing tests.
19    The SVC instruction below is for Cortex-M architectures using IAR tools. This will likely need to be modified
20    for different processors and/or development tools.
21 
22    Note also that for the Interrupt Processing test there is the assumption that the SVC ISR looks like:
23 
24     PUBLIC  SVC_Handler
25 SVC_Handler:
26     PUSH    {lr}
27     BL      tm_interrupt_handler
28     POP     {lr}
29     BX      LR
30 
31     And that for the Interrupt Preemption Processing test the SVC ISR looks like:
32 
33     PUBLIC  SVC_Handler
34 SVC_Handler:
35     PUSH    {lr}
36     BL      tm_interrupt_preemption_handler
37     POP     {lr}
38     BX      LR
39 
40    Again, this is very processor/tool specific so changes are likely needed for non Cortex-M/IAR
41    environments.  */
42 
43 #define TM_CAUSE_INTERRUPT    asm("SVC #0");
44 
45 
46 
47 #endif
48 
49