1/*
2 * init_caches2.S
3 *
4 *  Created on: March 30, 2012
5 *  Author: MIPS TECHNOLOGIES, INC
6 *  Common Cache initialization for a coherent processing system
7 *
8*/
9
10/*
11Unpublished work (c) MIPS Technologies, Inc.  All rights reserved.  Unpublished rights reserved
12under the copyright laws of the United States of America and other countries.
13
14This code is confidential and proprietary to MIPS Technologies, Inc. ("MIPS Technologies") and
15may be disclosed only as permitted in writing by MIPS Technologies or an authorized third party.
16Any copying, reproducing, modifying, use or disclosure of this code (in whole or in part) that is
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20
21MIPS Technologies reserves the right to change this code to improve function, design or
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36This code may only be disclosed to the United States government ("Government"), or to
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38party.  This code constitutes one or more of the following: commercial computer software,
39commercial computer software documentation or other commercial items.  If the user of this
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44Defense Federal Acquisition Regulation Supplement 227.7202 for military agencies.  The use of
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47Technologies or an authorized third party.
48*/
49
50#include <boot.h>
51#include <regdef.h>
52#include <m32c0.h>
53	.set	noreorder           // Don't allow the assembler to reorder instructions.
54	.set	noat                // Don't allow the assembler to use r1(at) for synthetic instr.
55
56/**************************************************************************************
57* init_icache invalidates all Instruction cache entries
58**************************************************************************************/
59
60LEAF(init_icache)
61
62	// For this Core there is always a I cache
63	// The IS field determines how may set there are
64	// IS = 2 there are 256 sets per way 1024 total
65	// IS = 3 there are 512 sets per way 2048 total
66
67	// v1 set to line size, will be used to increment through the cache tags
68	li		v1, 32 					// Line size is always 32 bytes.
69	mfc0	v0, C0_CONFIG1			// Read C0_Config1
70	ext	    a3, v0, CFG1_ILSHIFT, 3 		// Extract IS
71	li	    a2, 2		    		// Used to test against
72	beq		a2, a3, Isets_done	 	// if  IS = 2
73	li		a3, 1024					// sets = 256
74	li		a3, 2048 				// else sets = 512 Skipped if branch taken
75Isets_done:
76	lui	    a2, 0x8000				// Get a KSeg0 address for cacheops
77	// clear the lock bit, valid bit, and the LRF bit
78	mtc0    zero, C0_TAGLO			// Clear C0_ITagLo to invalidate entry
79
80next_icache_tag:
81	cache   0x8, 0(a2)				 // Index Store tag Cache opt
82	add	    a3, -1					 // Decrement set counter
83	bne     a3, zero, next_icache_tag // Done yet?
84	add     a2, v1		    	 // Increment line address by line size
85
86done_icache:
87
88    jr      ra
89    nop
90END(init_icache)
91
92/**************************************************************************************
93* init_dcache invalidates all data cache entries
94**************************************************************************************/
95
96LEAF(init_dcache)
97
98	// For this Core there is always a D cache
99	// The DS field determines how may set there are
100	// DS = 2 there are 256 sets per way 1024 total
101	// DS = 3 there are 512 sets per way 2048 total
102
103	// v1 set to line size, will be used to increment through the cache tags
104	li		v1, 32 					// Line size is always 32 bytes.
105	mfc0	v0, C0_CONFIG1			// Read C0_Config1
106	ext	    a3, v0, CFG1_DSSHIFT, 3 // Extract DS
107	li	    a2, 2		    		// Used to test against
108	beq		a2, a3, Dsets_done 		// if  DS = 2
109	li		a3, 1024				// sets = 256
110	li		a3, 2048 				// else sets = 512 Skipped if branch taken
111Dsets_done:
112	lui	    a2, 0x8000		    	// Get a KSeg0 address for cacheops
113	// clear the lock bit, valid bit, and the LRF bit
114	mtc0    zero, C0_TAGLO, 2		// Clear C0_DTagLo to invalidate entry
115
116next_dcache_tag:
117    cache	0x9, 0(a2)				 // Index Store tag Cache opt
118	add	    a3, -1		    		 // Decrement set counter
119	bne	    a3, zero, next_dcache_tag // Done yet?
120	add	    a2, v1	    			 // Increment line address by line size
121
122done_dcache:
123    jr      ra
124    nop
125END(init_dcache)
126
127/**************************************************************************************
128**************************************************************************************/
129LEAF(disable_L23)
130
131	bnez    r8_core_num, done_disable_L23	# Only done from core 0.
132
133    // Use CCA Override disable the L2 cache
134    // NOTE: If you have a L3 cache you must add code here
135    // to disable it or initialize it if it can't be disabled.
136    // Disable the L2 cache using CCA override by writing a 0x50 to
137    // the GCR Base register. 0x50 enables the CCA override bit and sets
138    // the CCA to uncached.
139
140	lw	    a0, 0x0008(r22_gcr_addr)  // Read GCR_BASE
141    li      a3, 0x50                  // Enable CCA and set to uncached
142    ins     a0, a3, 0, 8    // Insert bits
143    sw      a0, 0x0008(r22_gcr_addr)  // Write GCR_BASE
144
145done_disable_L23:
146    jr      ra
147    nop
148END(disable_L23)
149/**************************************************************************************
150* Initialize the L2 and L3 caches
151**************************************************************************************/
152LEAF(init_L23)
153
154	bnez    r8_core_num, done_cach_init			# Only done from core 0.
155
156	// L2 Cache initialization routine
157	// Check L2 cache size
158	mfc0	v0, C0_CONFIG2		// Read C0_Config2
159	// Isolate L2$ Line Size
160	ext	    v1, v0, 4, 4		// extract L2 line size
161	li	    a2, 2
162	sllv	v1, a2, v1			// Now have true L2$ line size in bytes
163
164	// Isolate L2 Sets per Way (cache lines per way)
165	ext	    a3, v0, 8, 4		// extrace sets per way encoding
166	li	    a2, 64
167	sllv	a3, a2, a3			// L2$ Sets per way
168
169	// Isolate L2 Associativity (number of ways)
170	// L2$ Assoc (-1)
171	ext	    a1, v0, 0, 4		// extract ways encoding
172	add	    a1, 1				// Decode L2 number of ways
173
174	mul	    a3, a3, a1			// Get total number of sets (sets per way * number of ways)
175
176	lui	    a2, 0x8000			// Get a KSeg0 address for cacheops
177
178	// Clear L23TagLo/L23TagHi registers these are used to set the cache tag
179	mtc0	zero, C0_TAGLO, 4
180	mtc0	zero, C0_TAGHI, 4
181
182	// L2$ Index Store Tag Cache Op
183	// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
184next_L2cache_tag:
185	cache	0xB, 0(a2)			// Write Tag using index store tag
186	add	    a3, -1				// Decrement set counter
187
188	bne	    a3, zero, next_L2cache_tag // Done yet?
189	add	    a2, v1				// Get next line address (each tag covers one line)
190
191
192	// Start of L3 cache initialization
193	// Isolate L3$ Line Size
194	ext	    v1, v0, CFG2_TLSHIFT, 4		// Extract L3 line size
195
196	// Skip ahead if No L3$
197	beq	    v1, zero, done_l3cache
198	nop
199
200	li	    a2, 2
201	sllv	v1, a2, v1			// Decode L3$ line size in bytes
202
203	// Isolate L3$ Sets per Way (cache lines per way)
204	ext	    a3, v0, CFG2_TSSHIFT, 4		// Extract L3 sets per way TDS encoding
205	li	    a2, 64
206	sllv	a3, a2, a3			// Decode L3 Sets per way
207
208	// Isolate L3$ Associativity (number of ways)
209	// L3$ Assoc (-1)
210	ext	    a1, v0, CFG2_TASHIFT, 4		// Extrace L3 associativity 2TA encoding
211	add	    a1, 1				// Decode L3 associativity (number of sets)
212	mul	    a3, a3, a1			// Compute total number of sets
213	lui	    a2, 0x8000		    // Get a KSeg0 address for cacheops
214
215	// Clear L23TagLo/L23TagHi registers
216	mtc0	zero, C0_TAGLO, 4
217	mtc0	zero, C0_TAGHI, 4
218
219	// L3 Index Store Tag Cache Op
220	// Will invalidate the tag entry, clear the lock bit, and clear the LRF bit
221next_L3cache_tag:
222	cache	0xA, 0(a2)			// TCIndexStTag
223	add	    a3, -1				// Decrement set counter
224	bne	    a3, zero, next_L3cache_tag
225	add	    a2, v1				// Get next line address
226
227done_l3cache:
228    // disable CCA Override to enable L2 cache
229	lw	    a0, 0x0008(r22_gcr_addr)  // GCR_BASE
230    ins     a0, zero, 0, 8            // CCA Override disabled
231    sw      a0, 0x0008(r22_gcr_addr)  // GCR_BASE
232
233done_cach_init:
234    jr      ra
235    nop
236END(init_L23)
237
238LEAF(change_k0_cca)
239	// NOTE! This code must be executed in KSEG1 (not KSGE0 uncached)
240    // Set CCA for kseg0 to cacheable
241	mfc0	v0, C0_CONFIG	// read C0_Config
242	beqz    r11_is_cps, set_kseg0_cca
243	li	    v1, 3			// CCA for non coherent core
244	li	    v1, 5			// CCA for coherent cores
245
246set_kseg0_cca:
247    ins	    v0, v1, 0, 3	// instert K0
248	mtc0	v0, C0_CONFIG	// write C0_Config
249	jr.hb      ra
250    nop
251
252END(change_k0_cca)
253