1/**************************************************************************/
2/*                                                                        */
3/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4/*                                                                        */
5/*       This software is licensed under the Microsoft Software License   */
6/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8/*       and in the root directory of this software.                      */
9/*                                                                        */
10/**************************************************************************/
11
12/**************************************************************************/
13/*   Copyright (c) Cadence Design Systems, Inc.                           */
14/*                                                                        */
15/* Permission is hereby granted, free of charge, to any person obtaining  */
16/* a copy of this software and associated documentation files (the        */
17/* "Software"), to deal in the Software without restriction, including    */
18/* without limitation the rights to use, copy, modify, merge, publish,    */
19/* distribute, sublicense, and/or sell copies of the Software, and to     */
20/* permit persons to whom the Software is furnished to do so, subject to  */
21/* the following conditions:                                              */
22/*                                                                        */
23/* The above copyright notice and this permission notice shall be         */
24/* included in all copies or substantial portions of the Software.        */
25/*                                                                        */
26/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,        */
27/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF     */
28/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
29/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY   */
30/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,   */
31/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE      */
32/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.                 */
33/**************************************************************************/
34
35/**************************************************************************/
36/**************************************************************************/
37/**                                                                       */
38/** ThreadX Component                                                     */
39/**                                                                       */
40/**   Thread                                                              */
41/**                                                                       */
42/**************************************************************************/
43/**************************************************************************/
44
45
46#include "xtensa_rtos.h"
47#include "tx_api_asm.h"
48
49    .text
50
51/**************************************************************************/
52/*                                                                        */
53/*  DESCRIPTION                                                           */
54/*                                                                        */
55/*    This function builds a stack frame on the supplied thread's stack.  */
56/*    The stack frame looks like an interrupt frame or a solicited frame  */
57/*    depending on the exception architecture of the target hardware.     */
58/*                                                                        */
59/*  RELEASE HISTORY                                                       */
60/*                                                                        */
61/*    DATE              NAME                      DESCRIPTION             */
62/*                                                                        */
63/*  12-31-2020     Cadence Design Systems   Initial Version 6.1.3         */
64/*                                                                        */
65/**************************************************************************/
66
67//  VOID   _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
68//  {
69    .globl  _tx_thread_stack_build
70    .type   _tx_thread_stack_build,@function
71    .align  4
72_tx_thread_stack_build:
73
74    ENTRY0
75
76    /* Get logical base of stack area (top). */
77    l32i    a5, a2, tx_thread_stack_end /* get top-1 of stack area */
78    addi    a5, a5, 1                   /* undo the -1 */
79    srli    a5, a5, 4                   /* force 16-byte alignment */
80    slli    a5, a5, 4                   /* a5 = post-dispatch SP (frame top) */
81
82    /* Allocate space for the frame (frame size is already 16-byte aligned). */
83    addi    a4, a5, -XT_STK_FRMSZ       /* a4 = pre-dispatch SP (frame base) */
84
85    /* Set the thread's SP. */
86    s32i    a4, a2, tx_thread_stack_ptr
87
88#if !XCHAL_HAVE_XEA2
89    addi    a4, a4, XT_STK_XTRA_SZ      /* a4 = base of exception frame */
90#endif
91
92    /* Clear the entire frame. (XEA3: only exception frame) */
93    movi    a6, 0                       /* a6 = 0 */
94    mov     a7, a4                      /* a7 = ptr to current word */
951:  s32i    a6, a7, 0                   /* clear current word */
96    addi    a7, a7, 4                   /* point to next word */
97    bltu    a7, a5, 1b                  /* repeat until frame top */
98
99#if XCHAL_HAVE_XEA2
100    s32i    a5, a4, XT_STK_A1           /* save post-dispatch SP in frame */
101#endif
102
103    /* Indicate a solicited or interrupted stack frame. */
104#if XCHAL_HAVE_XEA2
105    movi    a7, 0                       /* interrupted */
106#else
107    movi    a7, 0                       /* solicited */
108#endif
109    s32i    a7, a2, tx_thread_solicited
110
111    /*
112    Terminate GDB backtrace in this thread at the "return function" by ensuring
113    it's A0 == 0. Since frame was cleared, don't need to do this explicitly.
114    s32i    a6, a4, XT_STK_A0
115    */
116
117    /* Set the return address to the return function. */
118    /* Start thread via user exception exit dispatcher (could use any). */
119#if XCHAL_HAVE_XEA2
120    movi    a5, _xt_user_exit
121    s32i    a5, a4, XT_STK_EXIT
122#else
123    movi    a5, 0
124    s32i    a5, a4, XT_STK_ATOMCTL
125#endif
126
127    s32i    a3, a4, XT_STK_PC
128
129    /*
130    Set thread's initial PS for C code, all int levels enabled.
131    XEA2: Since we dispatch via level 1 (_xt_user_exit), must set PS.EXCM,
132      which will be cleared by 'rfe' after the dispatcher, to prevent
133      interrupts happening when PS is restored during the exit dispatcher.
134    XEA3: nothing special, other than setting the thread stack type.
135    */
136#if XCHAL_HAVE_XEA2
137    #ifdef __XTENSA_CALL0_ABI__
138    movi    a6, PS_UM | PS_EXCM
139    #else
140    movi    a6, PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1)  /* pretend 'call4' */
141    #endif
142#else
143    movi    a6, PS_STACK_FIRSTKER
144#endif
145    s32i    a6, a4, XT_STK_PS
146
147#if XCHAL_HAVE_XEA2
148    #ifdef XT_USE_SWPRI
149    /* Set the initial virtual priority mask value to all 1's */
150    movi    a3, -1
151    s32i    a3, a4, XT_STK_VPRI
152    #endif
153#endif
154
155    RET0
156
157//  }
158
159