1;/**************************************************************************/
2;/*                                                                        */
3;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4;/*                                                                        */
5;/*       This software is licensed under the Microsoft Software License   */
6;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8;/*       and in the root directory of this software.                      */
9;/*                                                                        */
10;/**************************************************************************/
11;
12;
13;/**************************************************************************/
14;/**************************************************************************/
15;/**                                                                       */
16;/** ThreadX Component                                                     */
17;/**                                                                       */
18;/**   Thread                                                              */
19;/**                                                                       */
20;/**************************************************************************/
21;/**************************************************************************/
22;
23
24    section .text:CODE:ROOT
25
26;/**************************************************************************/
27;/*                                                                        */
28;/*  FUNCTION                                               RELEASE        */
29;/*                                                                        */
30;/*    _tx_thread_stack_build                               RXv2/IAR       */
31;/*                                                           6.1.11       */
32;/*  AUTHOR                                                                */
33;/*                                                                        */
34;/*    William E. Lamie, Microsoft Corporation                             */
35;/*                                                                        */
36;/*  DESCRIPTION                                                           */
37;/*                                                                        */
38;/*    This function builds a stack frame on the supplied thread's stack.  */
39;/*    The stack frame results in a fake interrupt return to the supplied  */
40;/*    function pointer.                                                   */
41;/*                                                                        */
42;/*  INPUT                                                                 */
43;/*                                                                        */
44;/*    thread_ptr                            Pointer to thread control blk */
45;/*    function_ptr                          Pointer to return function    */
46;/*                                                                        */
47;/*  OUTPUT                                                                */
48;/*                                                                        */
49;/*    None                                                                */
50;/*                                                                        */
51;/*  CALLS                                                                 */
52;/*                                                                        */
53;/*    None                                                                */
54;/*                                                                        */
55;/*  CALLED BY                                                             */
56;/*                                                                        */
57;/*    _tx_thread_create                     Create thread service         */
58;/*                                                                        */
59;/*  RELEASE HISTORY                                                       */
60;/*                                                                        */
61;/*    DATE              NAME                      DESCRIPTION             */
62;/*                                                                        */
63;/*  12-30-2020     William E. Lamie         Initial Version 6.1.3         */
64;/*  10-15-2021     William E. Lamie         Modified comment(s), and      */
65;/*                                            removed unnecessary stack   */
66;/*                                            type placement,             */
67;/*                                            resulting in version 6.1.9  */
68;/*  01-31-2022     William E. Lamie         Modified comment(s),          */
69;/*                                            resulting in version 6.1.10 */
70;/*  04-25-2022     William E. Lamie         Modified comment(s),          */
71;/*                                            resulting in version 6.1.11 */
72;/*                                                                        */
73;/**************************************************************************/
74    public __tx_thread_stack_build
75__tx_thread_stack_build:
76;
77;
78;    /* Build an interrupt frame.  The form of the fake interrupt stack
79;       on the Renesas RX should look like the following after it is built:
80;
81;  Stack Top:           ACC0
82;                       ACC1
83;                       R6
84;                       R7
85;                       R8
86;                       R9
87;                       R10
88;                       R11
89;                       R12
90;                       R13
91;                       FPSW
92;                       R14
93;                       R15
94;                       R3
95;                       R4
96;                       R5
97;                       R1
98;                       R2
99;                       PC
100;                       PSW
101
102;
103;    Stack Bottom: (higher memory address)  */
104;
105    MOV.L   16[R1],R3                            ; Pickup end of stack area
106    BCLR    #0, R3                               ; Mask for 4-byte alignment
107    BCLR    #1, R3
108;
109;    /* Build the stack frame.  */
110;
111    MOV.L #30000h, R4
112    MOV.L R4, [-R3]                              ; Initial PSW (SVC mode, U flag set)
113    MOV.L R2, [-R3]                              ; Initial PC
114    MOV.L #0, R4
115    MOV.L R4,[-R3]                               ; Initial R2 ...
116    MOV.L R4,[-R3]                               ; Initial R1 ...
117    MOV.L R4,[-R3]                               ; Initial R5 ...
118    MOV.L R4,[-R3]                               ; Initial R4 ...
119    MOV.L R4,[-R3]                               ; Initial R3 ...
120    MOV.L R4,[-R3]                               ; Initial R15 ...
121    MOV.L R4,[-R3]                               ; Initial R14 ...
122    MVFC  FPSW, r4
123    MOV.L R4, [-R3]                              ; Initial FPSW
124    MOV.L #0, R4
125    MOV.L R4,[-R3]                               ; Initial R13 ...
126    MOV.L R4,[-R3]                               ; Initial R12 ...
127    MOV.L R4,[-R3]                               ; Initial R11 ...
128    MOV.L R4,[-R3]                               ; Initial R10 ...
129    MOV.L R4,[-R3]                               ; Initial R9 ...
130    MOV.L R4,[-R3]                               ; Initial R8 ...
131    MOV.L R4,[-R3]                               ; Initial R7 ...
132    MOV.L R4,[-R3]                               ; Initial R6 ...
133
134    MOV.L R4,[-R3]                               ; Accumulator 1
135    MOV.L R4,[-R3]
136    MOV.L R4,[-R3]
137
138    MOV.L R4,[-R3]                               ; Accumulator 0
139    MOV.L R4,[-R3]
140    MOV.L R4,[-R3]
141
142;    /* Setup stack pointer.  */
143;    thread_ptr -> tx_thread_stack_ptr =  R1;
144    MOV.L R3, 8[R1]
145                                                 ; Store initial SP in thread control block
146    RTS
147
148;}
149
150    END
151