1 Microsoft's Azure RTOS ThreadX for Cortex-M0 2 3 Using the GNU Tools 4 51. Building the ThreadX run-time Library 6 7First make sure you are in the "example_build" directory. Also, make sure that 8you have setup your path and other environment variables necessary for the ARM 9gnu (GNU) compiler. At this point you may run the build_threadx.bat batch file. 10This will build the ThreadX run-time environment in the "example_build" 11directory. 12 13You should observe assembly and compilation of a series of ThreadX source 14files. At the end of the batch file, they are all combined into the 15run-time library file: tx.a. This file must be linked with your 16application in order to use ThreadX. 17 18 192. Demonstration System for Cortex-M0 20 21The ThreadX demonstration is designed to execute on Cortex-M0 evaluation boards 22or on a dedicated simulator. 23 24Building the demonstration is easy, simply execute the build_threadx_sample.bat 25batch file while inside the "example_build" directory. 26 27You should observe the compilation of sample_threadx.c (which is the demonstration 28application) and linking with tx.a. The resulting file sample_threadx.out is a binary 29file that can be downloaded and executed on the a simulator, or downloaded to a board. 30 31 323. System Initialization 33 34The entry point in ThreadX for the Cortex-M0 using gnu tools uses the standard GNU 35Cortex-M0 reset sequence. From the reset vector the C runtime will be initialized. 36 37The ThreadX tx_initialize_low_level.S file is responsible for setting up 38various system data structures, the vector area, and a periodic timer interrupt 39source. 40 41In addition, _tx_initialize_low_level determines the first available 42address for use by the application, which is supplied as the sole input 43parameter to your application definition function, tx_application_define. 44 45 464. Register Usage and Stack Frames 47 48The following defines the saved context stack frames for context switches 49that occur as a result of interrupt handling or from thread-level API calls. 50All suspended threads have the same stack frame in the Cortex-M0 version of 51ThreadX. The top of the suspended thread's stack is pointed to by 52tx_thread_stack_ptr in the associated thread control block TX_THREAD. 53 54 55 Stack Offset Stack Contents 56 57 0x00 r8 58 0x04 r9 59 0x08 r10 60 0x0C r11 61 0x10 r4 62 0x14 r5 63 0x18 r6 64 0x1C r7 65 0x20 r0 (Hardware stack starts here!!) 66 0x24 r1 67 0x28 r2 68 0x2C r3 69 0x30 r12 70 0x34 lr 71 0x38 pc 72 0x3C xPSR 73 74 755. Improving Performance 76 77The distribution version of ThreadX is built without any compiler optimizations. 78This makes it easy to debug because you can trace or set breakpoints inside of 79ThreadX itself. Of course, this costs some performance. To make it run faster, 80you can change the build_threadx.bat file to remove the -g option and enable 81all compiler optimizations. 82 83In addition, you can eliminate the ThreadX basic API error checking by 84compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 85defined. 86 87 886. Interrupt Handling 89 90ThreadX provides complete and high-performance interrupt handling for Cortex-M0 91targets. There are a certain set of requirements that are defined in the 92following sub-sections: 93 94 956.1 Vector Area 96 97The Cortex-M0 vectors start at the label __tx_vectors or similar. The application may modify 98the vector area according to its needs. There is code in tx_initialize_low_level() that will 99configure the vector base register. 100 101 1026.2 Managed Interrupts 103 104ISRs can be written completely in C (or assembly language) without any calls to 105_tx_thread_context_save or _tx_thread_context_restore. These ISRs are allowed access to the 106ThreadX API that is available to ISRs. 107 108ISRs written in C will take the form (where "your_C_isr" is an entry in the vector table): 109 110void your_C_isr(void) 111{ 112 113 /* ISR processing goes here, including any needed function calls. */ 114} 115 116ISRs written in assembly language will take the form: 117 118 119 .global your_assembly_isr 120 .thumb_func 121your_assembly_isr: 122; VOID your_assembly_isr(VOID) 123; { 124 PUSH {r0, lr} 125; 126; /* Do interrupt handler work here */ 127; /* BL <your interrupt routine in C> */ 128 129 POP {r0, r1} 130 MOV lr, r1 131 BX lr 132; } 133 134 135Note: the Cortex-M0 requires exception handlers to be thumb labels, this implies bit 0 set. 136To accomplish this, the declaration of the label has to be preceded by the assembler directive 137.thumb_func to instruct the linker to create thumb labels. The label __tx_IntHandler needs to 138be inserted in the correct location in the interrupt vector table. This table is typically 139located in either your runtime startup file or in the tx_initialize_low_level.S file. 140 141 1427. Revision History 143 144For generic code revision information, please refer to the readme_threadx_generic.txt 145file, which is included in your distribution. The following details the revision 146information associated with this specific port of ThreadX: 147 14804-02-2021 Release 6.1.6 changes: 149 tx_port.h Updated macro definition 150 15103-02-2021 The following files were changed/added for version 6.1.5: 152 tx_thread_schedule.s Added low power feature 153 15409-30-2020 ThreadX update of Cortex-M0/GNU port. The following files were 155 changed/added for port specific version 6.1: 156 157 tx_initialize_low_level.S Comment out DWT code. 158 *.S Modified comments and whitespace. 159 16005/19/2020 Initial ThreadX 6.0 version for Cortex-M0 using GNU tools. 161 162 163Copyright(c) 1996-2020 Microsoft Corporation 164 165 166https://azure.com/rtos 167 168
