1;/**************************************************************************/ 2;/* */ 3;/* Copyright (c) Microsoft Corporation. All rights reserved. */ 4;/* */ 5;/* This software is licensed under the Microsoft Software License */ 6;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ 7;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ 8;/* and in the root directory of this software. */ 9;/* */ 10;/**************************************************************************/ 11; 12; 13;/**************************************************************************/ 14;/**************************************************************************/ 15;/** */ 16;/** ThreadX Component */ 17;/** */ 18;/** Thread */ 19;/** */ 20;/**************************************************************************/ 21;/**************************************************************************/ 22; 23; 24;#define TX_SOURCE_CODE 25; 26; 27;/* Include necessary system files. */ 28; 29;#include "tx_api.h" 30;#include "tx_thread.h" 31; 32FP .set A15 33DP .set B14 34SP .set B15 35ADDRESS_MSK .set 0xFFFFFFF0 36; 37 .sect ".text" 38;/**************************************************************************/ 39;/* */ 40;/* FUNCTION RELEASE */ 41;/* */ 42;/* _tx_thread_stack_build C667x/TI */ 43;/* 6.1 */ 44;/* AUTHOR */ 45;/* */ 46;/* William E. Lamie, Microsoft Corporation */ 47;/* */ 48;/* DESCRIPTION */ 49;/* */ 50;/* This function builds a stack frame on the supplied thread's stack. */ 51;/* The stack frame results in a fake interrupt return to the supplied */ 52;/* function pointer. */ 53;/* */ 54;/* INPUT */ 55;/* */ 56;/* thread_ptr Pointer to thread control blk */ 57;/* function_ptr Pointer to return function */ 58;/* */ 59;/* OUTPUT */ 60;/* */ 61;/* None */ 62;/* */ 63;/* CALLS */ 64;/* */ 65;/* None */ 66;/* */ 67;/* CALLED BY */ 68;/* */ 69;/* _tx_thread_create Create thread service */ 70;/* */ 71;/* RELEASE HISTORY */ 72;/* */ 73;/* DATE NAME DESCRIPTION */ 74;/* */ 75;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 76;/* */ 77;/**************************************************************************/ 78;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) 79;{ 80 .global _tx_thread_stack_build 81_tx_thread_stack_build: 82; 83; 84; /* Build a fake interrupt frame. The form of the fake interrupt stack 85; on the C667x should look like the following after it is built: 86; 87; Stack Top: N/A Available for use 88; 1 Interrupt stack frame type 4 89; CSR Initial value for CSR 8 90; IRP Initial thread entry 12 91; AMR Initial thread addressing mode 16 92; A0 Initial A0 20 93; A1 Initial A1 24 94; A2 Initial A2 28 95; A3 Initial A3 32 96; A4 Initial A4 36 97; A5 Initial A5 40 98; A6 Initial A6 44 99; A7 Initial A7 48 100; A8 Initial A8 52 101; A9 Initial A9 56 102; A10 Initial A10 60 103; A11 Initial A11 64 104; A12 Initial A12 68 105; A13 Initial A13 72 106; A14 Initial A14 76 107; A15 (FP) Initial A15 (FP) 80 108; B0 Initial B0 84 109; B1 Initial B1 88 110; B2 Initial B2 92 111; B3 Initial B3 96 112; B4 Initial B4 100 113; B5 Initial B5 104 114; B6 Initial B6 108 115; B7 Initial B7 112 116; B8 Initial B8 116 117; B9 Initial B9 120 118; B10 Initial B10 124 119; B11 Initial B11 128 120; B12 Initial B12 132 121; B13 Initial B13 136 122; A16 Initial A16 140 123; A17 Initial A17 144 124; A18 Initial A18 148 125; A19 Initial A19 152 126; A20 Initial A20 156 127; A21 Initial A21 160 128; A22 Initial A22 164 129; A23 Initial A23 168 130; A24 Initial A24 172 131; A25 Initial A25 176 132; A26 Initial A26 180 133; A27 Initial A27 184 134; A28 Initial A28 188 135; A29 Initial A29 192 136; A30 Initial A30 196 137; A31 Initial A31 200 138; B16 Initial B16 204 139; B17 Initial B17 208 140; B18 Initial B18 212 141; B19 Initial B19 216 142; B20 Initial B20 220 143; B21 Initial B21 224 144; B22 Initial B22 228 145; B23 Initial B23 232 146; B24 Initial B24 236 147; B25 Initial B25 240 148; B26 Initial B26 244 149; B27 Initial B27 248 150; B28 Initial B28 252 151; B29 Initial B29 256 152; B30 Initial B30 260 153; B31 Initial B31 264 154; ILC Initial ILC 268 155; RILC Initial RILC 272 156; ITSR Initial ITSR 276 157 158 159; 160; Stack Bottom: (higher memory address) */ 161; 162 LDW *+A4(16),A0 ; Pickup end of stack area 163 MVKL ADDRESS_MSK,A1 ; Build address mask 164 MVKH ADDRESS_MSK,A1 ; 165 MVC CSR,B0 ; Pickup current CSR 166 AND -2,B0,B0 ; Clear GIE bit 167 OR 2,B0,B0 ; Set PGIE bit for interrupt return 168 AND A1,A0,A0 ; Ensure alignment 169 MVKL 288,A2 ; Calculate stack size 170 SUB A0,A2,A0 ; Allocate space on thread's stack 171; 172; /* Actually build the stack frame. */ 173; 174 MVKL 1,A2 ; Build stack type 175 ZERO A3 ; Clear value 176 STW A2,*+A0(4) ; Interrupt stack type 177 STW B0,*+A0(8) ; Initial CSR 178 STW B4,*+A0(12) ; Thread shell entry point 179 STW A3,*+A0(16) ; Initial AMR 180 STW A3,*+A0(20) ; Initial A0 181 STW A3,*+A0(24) ; Initial A1 182 STW A3,*+A0(28) ; Initial A2 183 STW A3,*+A0(32) ; Initial A3 184 STW A3,*+A0(36) ; Initial A4 185 STW A3,*+A0(40) ; Initial A5 186 STW A3,*+A0(44) ; Initial A6 187 STW A3,*+A0(48) ; Initial A7 188 STW A3,*+A0(52) ; Initial A8 189 STW A3,*+A0(56) ; Initial A9 190 STW A3,*+A0(60) ; Initial A10 191 STW A3,*+A0(64) ; Initial A11 192 STW A3,*+A0(68) ; Initial A12 193 STW A3,*+A0(72) ; Initial A13 194 STW A3,*+A0(76) ; Initial A14 195 STW A3,*+A0(80) ; Initial A15 196 STW A3,*+A0(84) ; Initial B0 197 STW A3,*+A0(88) ; Initial B1 198 STW A3,*+A0(92) ; Initial B2 199 STW A3,*+A0(96) ; Initial B3 200 STW A3,*+A0(100) ; Initial B4 201 STW A3,*+A0(104) ; Initial B5 202 STW A3,*+A0(108) ; Initial B6 203 STW A3,*+A0(112) ; Initial B7 204 STW A3,*+A0(116) ; Initial B8 205 STW A3,*+A0(120) ; Initial B9 206 STW A3,*+A0(124) ; Initial B10 207 MVKL 128,A2 ; Stack adjustment value 208 ADD A2,A0,A2 ; Adjust pointer into stack frame 209 STW A3,*+A2(0) ; Initial B11 210 STW A3,*+A2(4) ; Initial B12 211 STW A3,*+A2(8) ; Initial B13 212 STW A3,*+A2(12) ; Initial A16 213 STW A3,*+A2(16) ; Initial A17 214 STW A3,*+A2(20) ; Initial A18 215 STW A3,*+A2(24) ; Initial A19 216 STW A3,*+A2(28) ; Initial A20 217 STW A3,*+A2(32) ; Initial A21 218 STW A3,*+A2(36) ; Initial A22 219 STW A3,*+A2(40) ; Initial A23 220 STW A3,*+A2(44) ; Initial A24 221 STW A3,*+A2(48) ; Initial A25 222 STW A3,*+A2(52) ; Initial A26 223 STW A3,*+A2(56) ; Initial A27 224 STW A3,*+A2(60) ; Initial A28 225 STW A3,*+A2(64) ; Initial A29 226 STW A3,*+A2(68) ; Initial A30 227 STW A3,*+A2(72) ; Initial A31 228 STW A3,*+A2(76) ; Initial B16 229 STW A3,*+A2(80) ; Initial B17 230 STW A3,*+A2(84) ; Initial B18 231 STW A3,*+A2(88) ; Initial B19 232 STW A3,*+A2(92) ; Initial B20 233 STW A3,*+A2(96) ; Initial B21 234 STW A3,*+A2(100) ; Initial B22 235 STW A3,*+A2(104) ; Initial B23 236 STW A3,*+A2(108) ; Initial B24 237 STW A3,*+A2(112) ; Initial B25 238 STW A3,*+A2(116) ; Initial B26 239 STW A3,*+A2(120) ; Initial B27 240 STW A3,*+A2(124) ; Initial B28 241 ADDK 128,A2 ; Adjust stack pointer again 242 STW A3,*+A2(0) ; Initial B29 243 STW A3,*+A2(4) ; Initial B30 244 STW A3,*+A2(8) ; Initial B31 245 B B3 ; Return to caller 246 STW A3,*+A2(12) ; Initial ILC 247 STW A3,*+A2(16) ; Initial RILC 248 MVKL 0x3,B0 ; Build initial ITSR (set GIE and SGIE bits) 249 STW B0,*+A2(20) ; Store ITSR 250; 251; /* Setup stack pointer. */ 252; thread_ptr -> tx_thread_stack_ptr = A0; 253; 254 STW A0,*+A4(8) ; Save stack pointer in thread's 255 ; control block 256;} 257 258