1;/**************************************************************************/
2;/*                                                                        */
3;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4;/*                                                                        */
5;/*       This software is licensed under the Microsoft Software License   */
6;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8;/*       and in the root directory of this software.                      */
9;/*                                                                        */
10;/**************************************************************************/
11;
12;
13;/**************************************************************************/
14;/**************************************************************************/
15;/**                                                                       */
16;/** ThreadX Component                                                     */
17;/**                                                                       */
18;/**   Thread                                                              */
19;/**                                                                       */
20;/**************************************************************************/
21;/**************************************************************************/
22;
23;
24;#define TX_SOURCE_CODE
25;
26;
27;/* Include necessary system files.  */
28;
29;#include "tx_api.h"
30;#include "tx_thread.h"
31;
32;
33    IF  :DEF:TX_ENABLE_FIQ_SUPPORT
34DISABLE_INTS    EQU     0xC0                    ; Disable IRQ & FIQ interrupts
35    ELSE
36DISABLE_INTS    EQU     0x80                    ; Disable IRQ interrupts
37    ENDIF
38MODE_MASK       EQU     0x1F                    ; Mode mask
39FIQ_MODE_BITS   EQU     0x11                    ; FIQ mode bits
40;
41;
42        AREA ||.text||, CODE, READONLY
43;/**************************************************************************/
44;/*                                                                        */
45;/*  FUNCTION                                               RELEASE        */
46;/*                                                                        */
47;/*    _tx_thread_fiq_nesting_end                           ARM9/AC5       */
48;/*                                                           6.1          */
49;/*  AUTHOR                                                                */
50;/*                                                                        */
51;/*    William E. Lamie, Microsoft Corporation                             */
52;/*                                                                        */
53;/*  DESCRIPTION                                                           */
54;/*                                                                        */
55;/*    This function is called by the application from FIQ mode after      */
56;/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */
57;/*    processing from system mode back to FIQ mode prior to the ISR       */
58;/*    calling _tx_thread_fiq_context_restore.  Note that this function    */
59;/*    assumes the system stack pointer is in the same position after      */
60;/*    nesting start function was called.                                  */
61;/*                                                                        */
62;/*    This function assumes that the system mode stack pointer was setup  */
63;/*    during low-level initialization (tx_initialize_low_level.s).        */
64;/*                                                                        */
65;/*    This function returns with FIQ interrupts disabled.                 */
66;/*                                                                        */
67;/*  INPUT                                                                 */
68;/*                                                                        */
69;/*    None                                                                */
70;/*                                                                        */
71;/*  OUTPUT                                                                */
72;/*                                                                        */
73;/*    None                                                                */
74;/*                                                                        */
75;/*  CALLS                                                                 */
76;/*                                                                        */
77;/*    None                                                                */
78;/*                                                                        */
79;/*  CALLED BY                                                             */
80;/*                                                                        */
81;/*    ISRs                                                                */
82;/*                                                                        */
83;/*  RELEASE HISTORY                                                       */
84;/*                                                                        */
85;/*    DATE              NAME                      DESCRIPTION             */
86;/*                                                                        */
87;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
88;/*                                                                        */
89;/**************************************************************************/
90;VOID   _tx_thread_fiq_nesting_end(VOID)
91;{
92    EXPORT  _tx_thread_fiq_nesting_end
93_tx_thread_fiq_nesting_end
94    MOV     r3,lr                               ; Save ISR return address
95    MRS     r0, CPSR                            ; Pickup the CPSR
96    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
97    MSR     CPSR_cxsf, r0                       ; Disable interrupts
98    LDMIA   sp!, {r1, lr}                       ; Pickup saved lr (and r1 throw-away for
99                                                ;   8-byte alignment logic)
100    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
101    ORR     r0, r0, #FIQ_MODE_BITS              ; Build IRQ mode CPSR
102    MSR     CPSR_cxsf, r0                       ; Re-enter IRQ mode
103    IF  {INTER} = {TRUE}
104    BX      r3                                  ; Return to caller
105    ELSE
106    MOV     pc, r3                              ; Return to caller
107    ENDIF
108;}
109;
110    END
111
112