1;/**************************************************************************/ 2;/* */ 3;/* Copyright (c) Microsoft Corporation. All rights reserved. */ 4;/* */ 5;/* This software is licensed under the Microsoft Software License */ 6;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ 7;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ 8;/* and in the root directory of this software. */ 9;/* */ 10;/**************************************************************************/ 11; 12; 13;/**************************************************************************/ 14;/**************************************************************************/ 15;/** */ 16;/** ThreadX Component */ 17;/** */ 18;/** Thread */ 19;/** */ 20;/**************************************************************************/ 21;/**************************************************************************/ 22; 23; 24;#define TX_SOURCE_CODE 25; 26; 27;/* Include necessary system files. */ 28; 29;#include "tx_api.h" 30;#include "tx_thread.h" 31; 32; 33SVC_MODE DEFINE 0x13 ; SVC mode 34#ifdef TX_ENABLE_FIQ_SUPPORT 35CPSR_MASK DEFINE 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled 36#else 37CPSR_MASK DEFINE 0x9F ; Mask initial CPSR, IRQ ints enabled 38#endif 39; 40; 41;/**************************************************************************/ 42;/* */ 43;/* FUNCTION RELEASE */ 44;/* */ 45;/* _tx_thread_stack_build ARM11/IAR */ 46;/* 6.1 */ 47;/* AUTHOR */ 48;/* */ 49;/* William E. Lamie, Microsoft Corporation */ 50;/* */ 51;/* DESCRIPTION */ 52;/* */ 53;/* This function builds a stack frame on the supplied thread's stack. */ 54;/* The stack frame results in a fake interrupt return to the supplied */ 55;/* function pointer. */ 56;/* */ 57;/* INPUT */ 58;/* */ 59;/* thread_ptr Pointer to thread control blk */ 60;/* function_ptr Pointer to return function */ 61;/* */ 62;/* OUTPUT */ 63;/* */ 64;/* None */ 65;/* */ 66;/* CALLS */ 67;/* */ 68;/* None */ 69;/* */ 70;/* CALLED BY */ 71;/* */ 72;/* _tx_thread_create Create thread service */ 73;/* */ 74;/* RELEASE HISTORY */ 75;/* */ 76;/* DATE NAME DESCRIPTION */ 77;/* */ 78;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 79;/* */ 80;/**************************************************************************/ 81;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) 82;{ 83 RSEG .text:CODE:NOROOT(2) 84 PUBLIC _tx_thread_stack_build 85 86 CODE32 87_tx_thread_stack_build 88; 89; 90; /* Build a fake interrupt frame. The form of the fake interrupt stack 91; on the ARM9 should look like the following after it is built: 92; 93; Stack Top: 1 Interrupt stack frame type 94; CPSR Initial value for CPSR 95; a1 (r0) Initial value for a1 96; a2 (r1) Initial value for a2 97; a3 (r2) Initial value for a3 98; a4 (r3) Initial value for a4 99; v1 (r4) Initial value for v1 100; v2 (r5) Initial value for v2 101; v3 (r6) Initial value for v3 102; v4 (r7) Initial value for v4 103; v5 (r8) Initial value for v5 104; sb (r9) Initial value for sb 105; sl (r10) Initial value for sl 106; fp (r11) Initial value for fp 107; ip (r12) Initial value for ip 108; lr (r14) Initial value for lr 109; pc (r15) Initial value for pc 110; 0 For stack backtracing 111; 112; Stack Bottom: (higher memory address) */ 113; 114 LDR r2, [r0, #16] ; Pickup end of stack area 115 BIC r2, r2, #7 ; Ensure long-word alignment 116 SUB r2, r2, #76 ; Allocate space for the stack frame 117; 118; /* Actually build the stack frame. */ 119; 120 MOV r3, #1 ; Build interrupt stack type 121 STR r3, [r2, #0] ; Store stack type 122 MOV r3, #0 ; Build initial register value 123 STR r3, [r2, #8] ; Store initial r0 124 STR r3, [r2, #12] ; Store initial r1 125 STR r3, [r2, #16] ; Store initial r2 126 STR r3, [r2, #20] ; Store initial r3 127 STR r3, [r2, #24] ; Store initial r4 128 STR r3, [r2, #28] ; Store initial r5 129 STR r3, [r2, #32] ; Store initial r6 130 STR r3, [r2, #36] ; Store initial r7 131 STR r3, [r2, #40] ; Store initial r8 132 STR r3, [r2, #44] ; Store initial r9 133 LDR r3, [r0, #12] ; Pickup stack starting address 134 STR r3, [r2, #48] ; Store initial r10 (sl) 135 MOV r3, #0 ; Build initial register value 136 STR r3, [r2, #52] ; Store initial r11 137 STR r3, [r2, #56] ; Store initial r12 138 STR r3, [r2, #60] ; Store initial lr 139 STR r1, [r2, #64] ; Store initial pc 140 STR r3, [r2, #68] ; 0 for back-trace 141 MRS r1, CPSR ; Pickup CPSR 142 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR 143 ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled 144 STR r3, [r2, #4] ; Store initial CPSR 145; 146; /* Setup stack pointer. */ 147; thread_ptr -> tx_thread_stack_ptr = r2; 148; 149 STR r2, [r0, #8] ; Save stack pointer in thread's 150 ; control block 151#ifdef TX_THUMB 152 BX lr ; Return to caller 153#else 154 MOV pc, lr ; Return to caller 155#endif 156;} 157 END 158 159
