1;/**************************************************************************/ 2;/* */ 3;/* Copyright (c) Microsoft Corporation. All rights reserved. */ 4;/* */ 5;/* This software is licensed under the Microsoft Software License */ 6;/* Terms for Microsoft Azure RTOS. Full text of the license can be */ 7;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */ 8;/* and in the root directory of this software. */ 9;/* */ 10;/**************************************************************************/ 11; 12; 13;/**************************************************************************/ 14;/**************************************************************************/ 15;/** */ 16;/** ThreadX Component */ 17;/** */ 18;/** Thread */ 19;/** */ 20;/**************************************************************************/ 21;/**************************************************************************/ 22; 23; 24;#define TX_SOURCE_CODE 25; 26; 27;/* Include necessary system files. */ 28; 29;#include "tx_api.h" 30;#include "tx_thread.h" 31; 32; 33SVC_MODE EQU 0x13 ; SVC mode 34 IF :DEF:TX_ENABLE_FIQ_SUPPORT 35CPSR_MASK EQU 0xDF ; Mask initial CPSR, IRQ & FIQ ints enabled 36 ELSE 37CPSR_MASK EQU 0x9F ; Mask initial CPSR, IRQ ints enabled 38 ENDIF 39; 40; 41 AREA ||.text||, CODE, READONLY 42;/**************************************************************************/ 43;/* */ 44;/* FUNCTION RELEASE */ 45;/* */ 46;/* _tx_thread_stack_build ARM11/AC5 */ 47;/* 6.1 */ 48;/* AUTHOR */ 49;/* */ 50;/* William E. Lamie, Microsoft Corporation */ 51;/* */ 52;/* DESCRIPTION */ 53;/* */ 54;/* This function builds a stack frame on the supplied thread's stack. */ 55;/* The stack frame results in a fake interrupt return to the supplied */ 56;/* function pointer. */ 57;/* */ 58;/* INPUT */ 59;/* */ 60;/* thread_ptr Pointer to thread control blk */ 61;/* function_ptr Pointer to return function */ 62;/* */ 63;/* OUTPUT */ 64;/* */ 65;/* None */ 66;/* */ 67;/* CALLS */ 68;/* */ 69;/* None */ 70;/* */ 71;/* CALLED BY */ 72;/* */ 73;/* _tx_thread_create Create thread service */ 74;/* */ 75;/* RELEASE HISTORY */ 76;/* */ 77;/* DATE NAME DESCRIPTION */ 78;/* */ 79;/* 09-30-2020 William E. Lamie Initial Version 6.1 */ 80;/* */ 81;/**************************************************************************/ 82;VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID)) 83;{ 84 EXPORT _tx_thread_stack_build 85_tx_thread_stack_build 86; 87; 88; /* Build a fake interrupt frame. The form of the fake interrupt stack 89; on the ARM11 should look like the following after it is built: 90; 91; Stack Top: 1 Interrupt stack frame type 92; CPSR Initial value for CPSR 93; a1 (r0) Initial value for a1 94; a2 (r1) Initial value for a2 95; a3 (r2) Initial value for a3 96; a4 (r3) Initial value for a4 97; v1 (r4) Initial value for v1 98; v2 (r5) Initial value for v2 99; v3 (r6) Initial value for v3 100; v4 (r7) Initial value for v4 101; v5 (r8) Initial value for v5 102; sb (r9) Initial value for sb 103; sl (r10) Initial value for sl 104; fp (r11) Initial value for fp 105; ip (r12) Initial value for ip 106; lr (r14) Initial value for lr 107; pc (r15) Initial value for pc 108; 0 For stack backtracing 109; 110; Stack Bottom: (higher memory address) */ 111; 112 LDR r2, [r0, #16] ; Pickup end of stack area 113 BIC r2, r2, #7 ; Ensure 8-byte alignment 114 SUB r2, r2, #76 ; Allocate space for the stack frame 115; 116; /* Actually build the stack frame. */ 117; 118 MOV r3, #1 ; Build interrupt stack type 119 STR r3, [r2, #0] ; Store stack type 120 MOV r3, #0 ; Build initial register value 121 STR r3, [r2, #8] ; Store initial r0 122 STR r3, [r2, #12] ; Store initial r1 123 STR r3, [r2, #16] ; Store initial r2 124 STR r3, [r2, #20] ; Store initial r3 125 STR r3, [r2, #24] ; Store initial r4 126 STR r3, [r2, #28] ; Store initial r5 127 STR r3, [r2, #32] ; Store initial r6 128 STR r3, [r2, #36] ; Store initial r7 129 STR r3, [r2, #40] ; Store initial r8 130 STR r3, [r2, #44] ; Store initial r9 131 LDR r3, [r0, #12] ; Pickup stack starting address 132 STR r3, [r2, #48] ; Store initial r10 (sl) 133 MOV r3, #0 ; Build initial register value 134 STR r3, [r2, #52] ; Store initial r11 135 STR r3, [r2, #56] ; Store initial r12 136 STR r3, [r2, #60] ; Store initial lr 137 STR r1, [r2, #64] ; Store initial pc 138 STR r3, [r2, #68] ; 0 for back-trace 139 MRS r1, CPSR ; Pickup CPSR 140 BIC r1, r1, #CPSR_MASK ; Mask mode bits of CPSR 141 ORR r3, r1, #SVC_MODE ; Build CPSR, SVC mode, interrupts enabled 142 STR r3, [r2, #4] ; Store initial CPSR 143; 144; /* Setup stack pointer. */ 145; thread_ptr -> tx_thread_stack_ptr = r2; 146; 147 STR r2, [r0, #8] ; Save stack pointer in thread's 148 ; control block 149 IF {INTER} = {TRUE} 150 BX lr ; Return to caller 151 ELSE 152 MOV pc, lr ; Return to caller 153 ENDIF 154;} 155 END 156 157
