1 Microsoft's Azure RTOS ThreadX for TMS320C667x 2 3 Using the TI Code Composer Tools 4 51. Installation 6 7TI Code Composer Studio and the TI MCSDK must be installed prior to 8building ThreadX. The following links can be used to download these 9packages: 10 11 12http://processors.wiki.ti.com/index.php/Download_CCS 13http://software-dl.ti.com/sdoemb/sdoemb_public_sw/bios_mcsdk/latest/index_FDS.html 14 15It is assumed the tools are installed in the default directories: 16 17CCS path by default - c:\ti\ccsv(version number) 18MCSDK path by default - c:\ti 19 20If the packages are installed in different directories, the ThreadX project 21settings must be adjusted. 22 232. Open the Azure RTOS Workspace 24 25In order to build the ThreadX library and the ThreadX demonstration first open 26the Azure RTOS Workspace inside your ThreadX installation directory. 27 28 293. Building the ThreadX run-time Library 30 31Building the ThreadX library is easy; simply import the CCS project file 32"tx" and then select the build button. You should now observe the compilation 33and assembly of the ThreadX library. This project build produces the ThreadX 34library file tx.lib. 35 36 374. Demonstration System 38 39The ThreadX demonstration is designed to execute on the C6678EVM evaluation board. 40 41Building the demonstration is easy; simply import the "sample_threadx_c6678evm" project. 42Now select "Project -> Build Active Project" to build the ThreadX demonstration, 43which produces the sample_threadx.out file in the "Debug" directory. You are now 44ready to run the ThreadX demonstration on the C6678EVM evaluation board. 45 46Please refer to Chapter 6 of the ThreadX User Guide for a complete description 47of this demonstration. 48 49 505. System Initialization 51 52The entry point in ThreadX for the TMS320C667x using the TI tools is at label 53_c_int00. This is defined within the TI library. In addition, this is 54where all static and global pre-set C variable initialization processing 55takes place. 56 57The ThreadX initialization file tx_initialize_low_level.asm is responsible 58for setting up various system data structures, the vector area, and a periodic 59timer interrupt source. By default, the vector area is defined to be located in 60the "vectors" section, which is defined at the top of tx_initialize_low_level.asm. 61This area is located at address 0 for the demonstration. 62 63tx_initialize_low_level.asm is also where initialization of a periodic timer 64interrupt source should take place. 65 66In addition, _tx_initialize_low_level determines the first available address 67for use by the application. By default, free memory is assumed to start after 68the .zend section in RAM (defined in tx_initialize_low_level). This section 69must be placed at the end of your other RAM sections. Please see sample_threadx.cmd 70for an example. The address of this section is passed to the application definition 71function, tx_application_define. 72 73 746. Register Usage and Stack Frames 75 76The TI TMS320C667x compiler assumes that registers A0-A9, A16-A31, B0-B9, and 77B16-B31 are scratch registers for each function. All other registers used by 78a C function must be preserved by the function. ThreadX takes advantage of this 79in situations where a context switch happens as a result of making a ThreadX 80service call (which is itself a C function). In such cases, the saved context 81of a thread is only the non-scratch registers. 82 83The following defines the saved context stack frames for context switches 84that occur as a result of interrupt handling or from thread-level API calls. 85All suspended threads have one of these two types of stack frames. The top 86of the suspended thread's stack is pointed to by tx_thread_stack_ptr in the 87associated thread control block TX_THREAD. 88 89 90 91 Offset Interrupted Stack Frame Non-Interrupt Stack Frame 92 93 0x04 1 0 94 0x08 CSR CSR 95 0x0C IPR B3 96 0x10 AMR AMR 97 0x14 A0 A10 98 0x18 A1 A11 99 0x1C A2 A12 100 0x20 A3 A13 101 0x24 A4 A14 102 0x28 A5 A15 103 0x2C A6 B10 104 0x30 A7 B11 105 0x34 A8 B12 106 0x38 A9 B13 107 0x3C A10 ILC 108 0x40 A11 RILC 109 0x44 A12 110 0x48 A13 111 0x4C A14 112 0x50 A15 113 0x54 B0 114 0x58 B1 115 0x5C B2 116 0x60 B3 117 0x64 B4 118 0x68 B5 119 0x6C B6 120 0x70 B7 121 0x74 B8 122 0x78 B9 123 0x7C B10 124 0x80 B11 125 0x84 B12 126 0x88 B13 127 0x8C A16 128 0x90 A17 129 0x94 A18 130 0x98 A19 131 0x9C A20 132 0xA0 A21 133 0xA4 A22 134 0xA8 A23 135 0xAC A24 136 0xB0 A25 137 0xB4 A26 138 0xB8 A27 139 0xBC A28 140 0xC0 A29 141 0xC4 A30 142 0xC8 A31 143 0xCC B16 144 0xD0 B17 145 0xD4 B18 146 0xD8 B19 147 0xDC B20 148 0xE0 B21 149 0xE4 B22 150 0xE8 B23 151 0xEC B24 152 0xF0 B25 153 0xF4 B26 154 0xF8 B27 155 0xFC B28 156 0x100 B29 157 0x104 B30 158 0x108 B31 159 0x10C ILC 160 0x110 RILC 161 0x114 ITSR 162 163 1647. Improving Performance 165 166The distribution version of ThreadX is built without any compiler 167optimizations. This makes it easy to debug because you can trace or set 168breakpoints inside of ThreadX itself. Of course, this costs some performance. 169To make it run faster, you can replace the -g compiler option 170to a -O3 in the ThreadX project file to enable all compiler optimizations. 171 172In addition, you can eliminate the ThreadX basic API error checking by 173compiling your application code with the symbol TX_DISABLE_ERROR_CHECKING 174defined. 175 176 1778. Interrupt Handling 178 179ThreadX provides complete and high-performance interrupt handling for 180TMS320C667x targets. There are a certain set of requirements that are 181defined in the following sub-sections: 182 183 1848.1 Vector Area 185 186The TMS320C667x interrupt vectors at in the section "vectors" and is defined at 187the top of tx_initialize_low_level.asm. Each interrupt vector entry contains 188a jump to a template interrupt processing shell. 189 190 1918.2 Interrupt Service Routine Shells 192 193The following interrupt processing shells are defined at the bottom of 194tx_initialize_low_level.asm: 195 196 197 __tx_int4_ISR 198 __tx_int5_ISR 199 __tx_int6_ISR 200 __tx_int7_ISR 201 __tx_int8_ISR 202 __tx_int9_ISR 203 __tx_int10_ISR 204 __tx_int11_ISR 205 __tx_int12_ISR 206 __tx_int13_ISR 207 __tx_int14_ISR 208 __tx_int15_ISR 209 210Each interrupt ISR is entered with B3, A0-A4 is available (these registers are 211saved in the initial vector processing). The default interrupt handling 212includes calls to __tx_thread_context_save and __tx_thread_context_restore. 213Application ISR processing can be added between the context save/restore 214calls. Note that only the compiler scratch registers are available for use 215after context save return to the ISR. 216 217High-frequency interrupt handlers might not want to perform context 218save/restore processing on each interrupt. If this is the case, any 219additional registers used must be saved and restored by the ISR and 220the interrupt return processing must restore the registers saved by the 221initial vector processing. This can be accomplished by adding the 222following code to the end of the custom ISR handling: 223 224 LDW *+SP(20),A0 ; Recover A0 225 LDW *+SP(24),A1 ; Recover A1 226 LDW *+SP(28),A2 ; Recover A2 227 LDW *+SP(32),A3 ; Recover A3 228 B IRP ; Return to point of interrupt 229|| LDW *+SP(36),A4 ; Recover A4 230 LDW *+SP(96),B3 ; Recover B3 231 ADDK.S2 288,SP ; Recover stack space 232 NOP 3 ; Delay slots 233 234 2359. Revision History 236 237For generic code revision information, please refer to the readme_threadx_generic.txt 238file, which is included in your distribution. The following details the revision 239information associated with this specific port of ThreadX: 240 24104-02-2021 Release 6.1.6 changes: 242 tx_port.h Updated macro definition 243 24409-30-2020 Initial ThreadX 6.1 version for TMS320C667x using TI Code Composer tools. 245 246 247Copyright(c) 1996-2020 Microsoft Corporation 248 249 250https://azure.com/rtos 251 252
