1;/**************************************************************************/
2;/*                                                                        */
3;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4;/*                                                                        */
5;/*       This software is licensed under the Microsoft Software License   */
6;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8;/*       and in the root directory of this software.                      */
9;/*                                                                        */
10;/**************************************************************************/
11;
12;
13;/**************************************************************************/
14;/**************************************************************************/
15;/**                                                                       */
16;/** ThreadX Component                                                     */
17;/**                                                                       */
18;/**   Thread                                                              */
19;/**                                                                       */
20;/**************************************************************************/
21;/**************************************************************************/
22;
23;
24;#define TX_SOURCE_CODE
25;
26;
27;/* Include necessary system files.  */
28;
29;#include "tx_api.h"
30;#include "tx_thread.h"
31;#include "tx_timer.h"
32;
33#ifdef TX_ENABLE_FIQ_SUPPORT
34DISABLE_INTS    DEFINE  0xC0                    ; Disable IRQ & FIQ interrupts
35#else
36DISABLE_INTS    DEFINE  0x80                    ; Disable IRQ interrupts
37#endif
38MODE_MASK       DEFINE  0x1F                    ; Mode mask
39FIQ_MODE_BITS   DEFINE  0x11                    ; FIQ mode bits
40;
41;
42;/**************************************************************************/
43;/*                                                                        */
44;/*  FUNCTION                                               RELEASE        */
45;/*                                                                        */
46;/*    _tx_thread_fiq_nesting_end                           ARM9/IAR       */
47;/*                                                           6.1          */
48;/*  AUTHOR                                                                */
49;/*                                                                        */
50;/*    William E. Lamie, Microsoft Corporation                             */
51;/*                                                                        */
52;/*  DESCRIPTION                                                           */
53;/*                                                                        */
54;/*    This function is called by the application from FIQ mode after      */
55;/*    _tx_thread_fiq_nesting_start has been called and switches the FIQ   */
56;/*    processing from system mode back to FIQ mode prior to the ISR       */
57;/*    calling _tx_thread_fiq_context_restore.  Note that this function    */
58;/*    assumes the system stack pointer is in the same position after      */
59;/*    nesting start function was called.                                  */
60;/*                                                                        */
61;/*    This function assumes that the system mode stack pointer was setup  */
62;/*    during low-level initialization (tx_initialize_low_level.s79).      */
63;/*                                                                        */
64;/*    This function returns with FIQ interrupts disabled.                 */
65;/*                                                                        */
66;/*  INPUT                                                                 */
67;/*                                                                        */
68;/*    None                                                                */
69;/*                                                                        */
70;/*  OUTPUT                                                                */
71;/*                                                                        */
72;/*    None                                                                */
73;/*                                                                        */
74;/*  CALLS                                                                 */
75;/*                                                                        */
76;/*    None                                                                */
77;/*                                                                        */
78;/*  CALLED BY                                                             */
79;/*                                                                        */
80;/*    ISRs                                                                */
81;/*                                                                        */
82;/*  RELEASE HISTORY                                                       */
83;/*                                                                        */
84;/*    DATE              NAME                      DESCRIPTION             */
85;/*                                                                        */
86;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
87;/*                                                                        */
88;/**************************************************************************/
89;VOID   _tx_thread_fiq_nesting_end(VOID)
90;{
91    RSEG    .text:CODE:NOROOT(2)
92    PUBLIC  _tx_thread_fiq_nesting_end
93    CODE32
94_tx_thread_fiq_nesting_end
95    MOV     r3,lr                               ; Save ISR return address
96    MRS     r0, CPSR                            ; Pickup the CPSR
97    ORR     r0, r0, #DISABLE_INTS               ; Build disable interrupt value
98    MSR     CPSR_cxsf, r0                       ; Disable interrupts
99    LDR     lr, [sp]                            ; Pickup saved lr
100    ADD     sp, sp, #4                          ; Adjust stack pointer
101    BIC     r0, r0, #MODE_MASK                  ; Clear mode bits
102    ORR     r0, r0, #FIQ_MODE_BITS              ; Build IRQ mode CPSR
103    MSR     CPSR_cxsf, r0                       ; Re-enter IRQ mode
104    MOV     pc, r3                              ; Return to ISR
105;}
106;
107;
108    END
109
110