1;/**************************************************************************/
2;/*                                                                        */
3;/*       Copyright (c) Microsoft Corporation. All rights reserved.        */
4;/*                                                                        */
5;/*       This software is licensed under the Microsoft Software License   */
6;/*       Terms for Microsoft Azure RTOS. Full text of the license can be  */
7;/*       found in the LICENSE file at https://aka.ms/AzureRTOS_EULA       */
8;/*       and in the root directory of this software.                      */
9;/*                                                                        */
10;/**************************************************************************/
11;
12;
13;/**************************************************************************/
14;/**************************************************************************/
15;/**                                                                       */
16;/** ThreadX Component                                                     */
17;/**                                                                       */
18;/**   Thread                                                              */
19;/**                                                                       */
20;/**************************************************************************/
21;/**************************************************************************/
22;
23;
24;#define TX_SOURCE_CODE
25;
26;
27;/* Include necessary system files.  */
28;
29;#include "tx_api.h"
30;#include "tx_thread.h"
31;
32;
33FIQ_DISABLE     EQU     0x40                    ; FIQ disable bit
34MODE_MASK       EQU     0x1F                    ; Mode mask
35SYS_MODE_BITS   EQU     0x1F                    ; System mode bits
36;
37;
38        AREA ||.text||, CODE, READONLY
39;/**************************************************************************/
40;/*                                                                        */
41;/*  FUNCTION                                               RELEASE        */
42;/*                                                                        */
43;/*    _tx_thread_fiq_nesting_start                        ARM11/AC5       */
44;/*                                                            6.1         */
45;/*  AUTHOR                                                                */
46;/*                                                                        */
47;/*    William E. Lamie, Microsoft Corporation                             */
48;/*                                                                        */
49;/*  DESCRIPTION                                                           */
50;/*                                                                        */
51;/*    This function is called by the application from FIQ mode after      */
52;/*    _tx_thread_fiq_context_save has been called and switches the FIQ    */
53;/*    processing to the system mode so nested FIQ interrupt processing    */
54;/*    is possible (system mode has its own "lr" register).  Note that     */
55;/*    this function assumes that the system mode stack pointer was setup  */
56;/*    during low-level initialization (tx_initialize_low_level.s).        */
57;/*                                                                        */
58;/*    This function returns with FIQ interrupts enabled.                  */
59;/*                                                                        */
60;/*  INPUT                                                                 */
61;/*                                                                        */
62;/*    None                                                                */
63;/*                                                                        */
64;/*  OUTPUT                                                                */
65;/*                                                                        */
66;/*    None                                                                */
67;/*                                                                        */
68;/*  CALLS                                                                 */
69;/*                                                                        */
70;/*    None                                                                */
71;/*                                                                        */
72;/*  CALLED BY                                                             */
73;/*                                                                        */
74;/*    ISRs                                                                */
75;/*                                                                        */
76;/*  RELEASE HISTORY                                                       */
77;/*                                                                        */
78;/*    DATE              NAME                      DESCRIPTION             */
79;/*                                                                        */
80;/*  09-30-2020     William E. Lamie         Initial Version 6.1           */
81;/*                                                                        */
82;/**************************************************************************/
83;VOID   _tx_thread_fiq_nesting_start(VOID)
84;{
85    EXPORT  _tx_thread_fiq_nesting_start
86_tx_thread_fiq_nesting_start
87    MOV     r3,lr                               ; Save ISR return address
88    MRS     r0, CPSR                            ; Pickup the CPSR
89    BIC     r0, r0, #MODE_MASK                  ; Clear the mode bits
90    ORR     r0, r0, #SYS_MODE_BITS              ; Build system mode CPSR
91    MSR     CPSR_cxsf, r0                       ; Enter system mode
92    STMDB   sp!, {r1, lr}                       ; Push the system mode lr on the system mode stack
93                                                ;   and push r1 just to keep 8-byte alignment
94    BIC     r0, r0, #FIQ_DISABLE                ; Build enable FIQ CPSR
95    MSR     CPSR_cxsf, r0                       ; Enter system mode
96    IF  {INTER} = {TRUE}
97    BX      r3                                  ; Return to caller
98    ELSE
99    MOV     pc, r3                              ; Return to caller
100    ENDIF
101;}
102;
103    END
104
105