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/ThreadX-v6.4.1/ports_module/cortex_r4/ac6/module_manager/src/
Dtx_thread_interrupt_control.S32 #define INT_MASK 0xC0 // Interrupt bit mask macro
34 #define INT_MASK 0x80 // Interrupt bit mask macro
92 BIC r1, r3, #INT_MASK // Clear interrupt lockout bits
98 AND r0, r3, #INT_MASK // Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_r4/ac6/src/
Dtx_thread_interrupt_control.S32 #define INT_MASK 0xC0 // Interrupt bit mask macro
34 #define INT_MASK 0x80 // Interrupt bit mask macro
92 BIC r1, r3, #INT_MASK // Clear interrupt lockout bits
98 AND r0, r3, #INT_MASK // Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_interrupt_control.s23 INT_MASK EQU 0xC0 // Interrupt bit mask define
25 INT_MASK EQU 0x80 // Interrupt bit mask define
75 BIC r1, r3, #INT_MASK // Clear interrupt lockout bits
81 AND r0, r3, #INT_MASK // Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_interrupt_control.S32 INT_MASK = 0xC0 @ Interrupt bit mask define
34 INT_MASK = 0x80 @ Interrupt bit mask define
88 BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits
94 AND r0, r3, #INT_MASK @ Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/src/
Dtx_thread_interrupt_control.S32 INT_MASK = 0xC0 @ Interrupt bit mask define
34 INT_MASK = 0x80 @ Interrupt bit mask define
88 BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits
94 AND r0, r3, #INT_MASK @ Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_interrupt_control.S32 INT_MASK = 0xC0 @ Interrupt bit mask define
34 INT_MASK = 0x80 @ Interrupt bit mask define
88 BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits
94 AND r0, r3, #INT_MASK @ Return previous interrupt mask
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a7/iar/src/
Dtx_thread_interrupt_control.s32 INT_MASK DEFINE 0xC0 ; Interrupt bit mask label
34 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
92 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/arm11/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/arm9/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_r4/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_r5/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a8/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a9/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a5/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports/cortex_a7/ac5/src/
Dtx_thread_interrupt_control.s32 INT_MASK EQU 0xC0 ; Interrupt bit mask define
34 INT_MASK EQU 0x80 ; Interrupt bit mask define
85 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
91 AND r0, r3, #INT_MASK ; Return previous interrupt mask
/ThreadX-v6.4.1/ports_module/cortex_r4/iar/module_manager/src/
Dtx_thread_interrupt_control.s24 INT_MASK DEFINE 0x80 ; Interrupt bit mask label
75 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
81 AND r0, r3, #INT_MASK ; Return previous interrupt mask

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