| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/gnu/example_build/ |
| D | init_cp0.S | 65 beq v1, zero, done_wr
72 mtc0 zero, C0_WATCHLO // write C0_WatchLo0
77 mtc0 zero, C0_WATCHLO, 1 // write C0_WatchLo1
82 mtc0 zero, C0_WATCHLO, 2 // write C0_WatchLo2
87 mtc0 zero, C0_WATCHLO, 3 // write C0_WatchLo3
92 mtc0 zero, C0_WATCHLO, 4 // write C0_WatchLo4
97 mtc0 zero, C0_WATCHLO, 5 // write C0_WatchLo5
102 mtc0 zero, C0_WATCHLO, 6 // write C0_WatchLo6
105 mtc0 zero, C0_WATCHLO, 7 // write C0_WatchLo7
115 mtc0 zero, C0_COMPARE // write C0_Compare
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| D | init_caches2.S | 78 mtc0 zero, C0_TAGLO // Clear C0_ITagLo to invalidate entry
83 bne a3, zero, next_icache_tag // Done yet?
114 mtc0 zero, C0_TAGLO, 2 // Clear C0_DTagLo to invalidate entry
119 bne a3, zero, next_dcache_tag // Done yet?
179 mtc0 zero, C0_TAGLO, 4
180 mtc0 zero, C0_TAGHI, 4
188 bne a3, zero, next_L2cache_tag // Done yet?
197 beq v1, zero, done_l3cache
216 mtc0 zero, C0_TAGLO, 4
217 mtc0 zero, C0_TAGHI, 4
[all …]
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| D | init_tlb.S | 69 mtc0 zero, C0_ENTRYLO0 // write C0_EntryLo0
70 mtc0 zero, C0_ENTRYLO1 // write C0_EntryLo1
71 mtc0 zero, C0_PAGEMASK // write C0_PageMask
72 mtc0 zero, C0_WIRED // write C0_Wired
82 bne v1, zero, next_tlb_entry_pair
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| D | init_L23caches.S | 129 beq v1, zero, done_l2cache
150 mtc0 zero, C0_TAGLO, 4
160 bne a3, zero, next_L2cache_tag // Done yet?
169 beq v1, zero, done_l3cache
189 mtc0 zero, C0_TAGLO, 4
199 bne a3, zero, next_L3cache_tag
207 ins a0, zero, 0, 8 // CCA Override disabled
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| D | init_vpe1.S | 92 move a3_TC, zero
189 ins v0, zero, 15, 1 // clear TE
198 ins v0, zero, 0, 1 // insert VPA
224 ins a1, zero, 29, 1 // Convert to cached kseg0 address in case we linked to kseg1.
229 ins v0, zero, 10, 1 // insert IXMT
233 mttc0 zero, C0_TCHALT // write C0_TCHALT
249 ins v0, zero, 1, 1 // insert VPC
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| D | copy_c2_ram.S | 93 sw zero, 0(a1_temp_addr)
106 sw zero, 0(a1_temp_addr)
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| D | regdef.h | 4 #define zero $0 /* wired zero */ macro
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| D | init_cpc.S | 64 move r30_cpc_addr, zero
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| D | join_domain.S | 70 move a3, zero
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| D | release_mp.S | 82 sw zero, 0x4000(r22_gcr_addr) // GCR_CO_RESET_RELEASE
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| /ThreadX-v6.3.0/ports_smp/arc_hs_smp/metaware/src/ |
| D | tx_thread_smp_unprotect.s | 87 breq r6, 0, _still_protected ; If zero, protection is still active
90 brne r6, 0, _still_protected ; If non-zero, protection is still active
92 brne r6, 0, _still_protected ; If non-zero, don't release the protection
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| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/gnu/src/ |
| D | tx_thread_smp_unprotect.S | 80 beq $12, $0, _still_protected # If zero, protection is not in force anymore
83 bne $12, $0, _still_protected # If non-zero, nested protection condition
|
| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | init_cp0.mip | 65 beq v1, zero, done_wr
72 mtc0 zero, C0_WATCHLO // write C0_WatchLo0
77 mtc0 zero, C0_WATCHLO, 1 // write C0_WatchLo1
82 mtc0 zero, C0_WATCHLO, 2 // write C0_WatchLo2
87 mtc0 zero, C0_WATCHLO, 3 // write C0_WatchLo3
92 mtc0 zero, C0_WATCHLO, 4 // write C0_WatchLo4
97 mtc0 zero, C0_WATCHLO, 5 // write C0_WatchLo5
102 mtc0 zero, C0_WATCHLO, 6 // write C0_WatchLo6
105 mtc0 zero, C0_WATCHLO, 7 // write C0_WatchLo7
115 mtc0 zero, C0_COMPARE // write C0_Compare
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| D | init_caches2.mip | 78 mtc0 zero, C0_TAGLO // Clear C0_ITagLo to invalidate entry
83 bne a3, zero, next_icache_tag // Done yet?
114 mtc0 zero, C0_TAGLO, 2 // Clear C0_DTagLo to invalidate entry
119 bne a3, zero, next_dcache_tag // Done yet?
179 mtc0 zero, C0_TAGLO, 4
180 mtc0 zero, C0_TAGHI, 4
188 bne a3, zero, next_L2cache_tag // Done yet?
197 beq v1, zero, done_l3cache
216 mtc0 zero, C0_TAGLO, 4
217 mtc0 zero, C0_TAGHI, 4
[all …]
|
| D | regdef.h | 4 #define zero $0 /* wired zero */ macro
|
| D | init_tlb.mip | 69 mtc0 zero, C0_ENTRYLO0 // write C0_EntryLo0
70 mtc0 zero, C0_ENTRYLO1 // write C0_EntryLo1
71 mtc0 zero, C0_PAGEMASK // write C0_PageMask
72 mtc0 zero, C0_WIRED // write C0_Wired
82 bne v1, zero, next_tlb_entry_pair
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| /ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/src/ |
| D | tx_thread_smp_unprotect.mip | 43 /* and _tx_thread_preempt_disable are both zero, then multithreading */
80 beq $12, $0, _still_protected # If zero, protection is not in force anymore
83 bne $12, $0, _still_protected # If non-zero, nested protection condition
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| /ThreadX-v6.3.0/ports_module/cortex_a35_smp/ac6/module_lib/src/ |
| D | txm_module_initialize.S | 65 .zero TXM_MODULE_HEAP_SIZE
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| /ThreadX-v6.3.0/ports_module/cortex_a35/ac6/module_lib/src/ |
| D | txm_module_initialize.S | 65 .zero TXM_MODULE_HEAP_SIZE
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| /ThreadX-v6.3.0/ports_smp/cortex_a5x_smp/green/src/ |
| D | tx_thread_smp_unprotect.a64 | 53 /* and _tx_thread_preempt_disable are both zero, then multithreading */
92 …B.EQ _still_protected // If the protection count is zero, protection has alr…
97 …B.NE _still_protected // If the protection count is non-zero, protection is …
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| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/src/ |
| D | tx_thread_smp_unprotect.s | 104 …BEQ _still_protected @ If the protection count is zero, protection has alre…
109 …BNE _still_protected @ If the protection count is non-zero, protection is s…
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/src/ |
| D | tx_thread_smp_unprotect.S | 104 …BEQ _still_protected @ If the protection count is zero, protection has alre…
109 …BNE _still_protected @ If the protection count is non-zero, protection is s…
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| /ThreadX-v6.3.0/ports/arc_em/metaware/src/ |
| D | tx_timer_interrupt.s | 104 breq r2, 0, __tx_timer_no_time_slice ; If zero, no time-slice is active
115 brne r2, 0, __tx_timer_no_time_slice ; If non-zero, skip over expiration
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| /ThreadX-v6.3.0/ports/arc_hs/metaware/src/ |
| D | tx_timer_interrupt.s | 104 breq r2, 0, __tx_timer_no_time_slice ; If zero, no time-slice is active
115 brne r2, 0, __tx_timer_no_time_slice ; If non-zero, skip over expiration
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| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/src/ |
| D | tx_thread_smp_unprotect.S | 104 …BEQ _still_protected @ If the protection count is zero, protection has alre…
109 …BNE _still_protected @ If the protection count is non-zero, protection is s…
|
