| /ThreadX-v6.3.0/ports/arc_hs/metaware/src/ |
| D | tx_thread_register_bank_assign.s | 90 ld r5, [r4, 164] ; Pickup initial status32 from stack area
92 st r5, [r4, 164] ; Store initial status32 in stack area
|
| /ThreadX-v6.3.0/ports/c667x/ccs/src/ |
| D | tx_thread_stack_build.asm | 162 LDW *+A4(16),A0 ; Pickup end of stack area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/example_build/ |
| D | tx_initialize_low_level.S | 97 LDR r0, =_end @ Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/ports_module/cortex_r4/iar/module_manager/src/ |
| D | txm_module_manager_thread_stack_build.s | 102 LDR r2, [r0, #16] ; Pickup end of stack area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/gnu/example_build/ |
| D | tx_initialize_low_level.s | 97 LDR r0, =_end @ Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/ |
| D | tx_initialize_low_level.s | 94 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/src/ |
| D | tx_initialize_low_level.s | 94 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/ports_module/cortex_a7/iar/module_manager/src/ |
| D | txm_module_manager_thread_stack_build.s | 112 LDR r2, [r0, #16] ; Pickup end of stack area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | tx_initialize_low_level.s | 94 LDR r0, =||Image$$SHARED_DATA$$ZI$$Limit|| ; Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/utility/rtos_compatibility_layers/OSEK/ |
| D | tx_osek.c | 747 ULONG area; in ActivateTask() local
756 area = osek_task_independent_area(); in ActivateTask()
757 if(area != TX_TRUE) in ActivateTask()
905 ULONG area; in TerminateTask() local
914 area = osek_task_independent_area(); in TerminateTask()
915 if(area != TX_TRUE) in TerminateTask()
1081 ULONG area; in ChainTask() local
1088 area = osek_task_independent_area(); in ChainTask()
1089 if(area != TX_TRUE) in ChainTask()
1348 ULONG area; in GetTaskState() local
[all …]
|
| /ThreadX-v6.3.0/ports_module/cortex_a7/ac5/module_manager/src/ |
| D | txm_module_manager_thread_stack_build.s | 114 LDR r2, [r0, #16] ; Pickup end of stack area
|
| /ThreadX-v6.3.0/ports_smp/cortex_a9_smp/gnu/ |
| D | readme_threadx.txt | 40 various system data structures, the vector area, and a periodic timer interrupt
41 source. By default, the vector area is defined to be located in the Init area,
42 which is defined at the top of tx_initialize_low_level.s. This area is typically
44 of the Init area should be copied to address 0.
115 Init area contains the vectors and is loaded at address zero. On actual
116 hardware platforms, this area might have to be copied to address 0.
|
| /ThreadX-v6.3.0/ports/cortex_m3/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-M3 vector area. */
|
| D | sample_threadx.ld | 12 # sdabase - base of the small data area section pointer
|
| D | sample_threadx_el.ld | 12 # sdabase - base of the small data area section pointer
|
| /ThreadX-v6.3.0/ports/cortex_m4/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-M4 vector area. */
|
| /ThreadX-v6.3.0/ports/cortex_m7/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-M7 vector area. */
|
| /ThreadX-v6.3.0/ports_smp/cortex_a7_smp/gnu/example_build/ |
| D | tx_initialize_low_level.S | 120 LDR r1, =_end @ Get end of non-initialized RAM area
|
| /ThreadX-v6.3.0/ports/cortex_a8/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-A8 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_a9/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-A9 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_r5/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-R5 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_r7/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-R7 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_r4/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-R4 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_a7/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-A7 vector area. This should be located or copied to 0. */
|
| /ThreadX-v6.3.0/ports/cortex_a5/ghs/example_build/ |
| D | reset.arm | 3 #/* Define the Cortex-A5 vector area. This should be located or copied to 0. */
|
