| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/ |
| D | init_cp0.S | 59 li v1, 0x00000404 // (M_StatusIM | M_StatusERL)
60 mtc0 v1, C0_STATUS // write C0_Status
64 ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
65 beq v1, zero, done_wr
66 li v1, 0x7 // (M_WatchHiI | M_WatchHiR | M_WatchHiW)
69 mtc0 v1, C0_WATCHHI // write C0_WatchHi0
74 mtc0 v1, C0_WATCHHI, 1 // write C0_WatchHi1
79 mtc0 v1, C0_WATCHHI, 2 // write C0_WatchHi2
84 mtc0 v1, C0_WATCHHI, 3 // write C0_WatchHi3
89 mtc0 v1, C0_WATCHHI, 4 // write C0_WatchHi4
[all …]
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| D | init_tlb.S | 59 mfc0 v1, C0_CONFIG // read C0_Config
60 ext v1, v1, 7, 3 // extract MT field
62 bne v1, a3, done_init_tlb
68 ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
76 mtc0 v1, C0_INDEX // write C0_Index
82 bne v1, zero, next_tlb_entry_pair
83 add v1, -1
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| D | init_caches2.S | 68 li v1, 32 // Line size is always 32 bytes.
84 add a2, v1 // Increment line address by line size
104 li v1, 32 // Line size is always 32 bytes.
120 add a2, v1 // Increment line address by line size
160 ext v1, v0, 4, 4 // extract L2 line size
162 sllv v1, a2, v1 // Now have true L2$ line size in bytes
189 add a2, v1 // Get next line address (each tag covers one line)
194 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
197 beq v1, zero, done_l3cache
201 sllv v1, a2, v1 // Decode L3$ line size in bytes
[all …]
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| D | init_L23caches.S | 126 ext v1, v0, 4, 4 // extract SL
129 beq v1, zero, done_l2cache
133 sllv v1, a2, v1 // Now have true L2$ line size in bytes
161 add a2, v1 // Get next line address
166 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
169 beq v1, zero, done_l3cache
173 sllv v1, a2, v1 // Decode L3$ line size in bytes
200 add a2, v1 // Get next line address
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| D | init_vpe1.S | 109 move v1, a3_TC
112 ins v0, v1, 0, 4 // change S_TCBindCurVPE
120 slt v1, a2_NVPES, a3_TC
121 bnez v1, 2f // Bind spare a3_TC's to VPElast
122 move v1, a2_NVPES
129 move v1, a3_TC
133 ins v0, v1, 0, 4 // insert VPE
183 slt v1, a2_NVPES, a3_TC
184 bnez v1, donevpe // No more VPE's
242 sltu v1, a0_NTCS, a3_TC
[all …]
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| D | start.S | 199 li v1, 0x20
200 sw v1, 1048(v0)
201 sw v1, 1056(v0)
202 sw v1, 1064(v0)
203 sw v1, 1072(v0)
204 sw v1, 1080(v0)
205 sw v1, 1088(v0)
206 sw v1, 1096(v0)
207 sw v1, 1104(v0)
216 mfc0 v1, C0_CONFIG // read C0_Config
[all …]
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| D | regdef.h | 7 #define v1 $3 macro
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| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | init_cp0.mip | 58 // li v1, 0x00400404 // (M_StatusIM | M_StatusERL | M_StatusBEV)
59 li v1, 0x00000404 // (M_StatusIM | M_StatusERL)
60 mtc0 v1, C0_STATUS // write C0_Status
64 ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
65 beq v1, zero, done_wr
66 li v1, 0x7 // (M_WatchHiI | M_WatchHiR | M_WatchHiW)
69 mtc0 v1, C0_WATCHHI // write C0_WatchHi0
74 mtc0 v1, C0_WATCHHI, 1 // write C0_WatchHi1
79 mtc0 v1, C0_WATCHHI, 2 // write C0_WatchHi2
84 mtc0 v1, C0_WATCHHI, 3 // write C0_WatchHi3
[all …]
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| D | init_caches2.mip | 67 // v1 set to line size, will be used to increment through the cache tags
68 li v1, 32 // Line size is always 32 bytes.
84 add a2, v1 // Increment line address by line size
103 // v1 set to line size, will be used to increment through the cache tags
104 li v1, 32 // Line size is always 32 bytes.
120 add a2, v1 // Increment line address by line size
160 ext v1, v0, 4, 4 // extract L2 line size
162 sllv v1, a2, v1 // Now have true L2$ line size in bytes
189 add a2, v1 // Get next line address (each tag covers one line)
194 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
[all …]
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| D | init_tlb.mip | 59 mfc0 v1, C0_CONFIG // read C0_Config
60 ext v1, v1, 7, 3 // extract MT field
62 bne v1, a3, done_init_tlb
68 ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
76 mtc0 v1, C0_INDEX // write C0_Index
82 bne v1, zero, next_tlb_entry_pair
83 add v1, -1
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| D | init_L23caches.mip | 126 ext v1, v0, 4, 4 // extract SL
129 beq v1, zero, done_l2cache
133 sllv v1, a2, v1 // Now have true L2$ line size in bytes
161 add a2, v1 // Get next line address
166 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
169 beq v1, zero, done_l3cache
173 sllv v1, a2, v1 // Decode L3$ line size in bytes
200 add a2, v1 // Get next line address
|
| D | init_vpe1.mip | 109 move v1, a3_TC
112 ins v0, v1, 0, 4 // change S_TCBindCurVPE
120 slt v1, a2_NVPES, a3_TC
121 bnez v1, 2f // Bind spare a3_TC's to VPElast
122 move v1, a2_NVPES
129 move v1, a3_TC
133 ins v0, v1, 0, 4 // insert VPE
183 slt v1, a2_NVPES, a3_TC
184 bnez v1, donevpe // No more VPE's
242 sltu v1, a0_NTCS, a3_TC
[all …]
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| D | regdef.h | 7 #define v1 $3 macro
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| D | start.mip | 199 li v1, 0x20
200 sw v1, 1048(v0)
201 sw v1, 1056(v0)
202 sw v1, 1064(v0)
203 sw v1, 1072(v0)
204 sw v1, 1080(v0)
205 sw v1, 1088(v0)
206 sw v1, 1096(v0)
207 sw v1, 1104(v0)
216 mfc0 v1, C0_CONFIG // read C0_Config
[all …]
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| /ThreadX-v6.4.1/ports/cortex_r4/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
173 LDMIA sp!, {v1-r11, lr} # Otherwise, return to thread synchronously
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| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/ |
| D | tx_thread_context_save.S | 159 sw $3, 104($29) # Store v1
248 sw $3, 104($29) # Store v1
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| D | tx_thread_stack_build.S | 184 sw $0, 104($8) # Initial v1
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| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/ |
| D | tx_thread_stack_build.mip | 102 $3 (104) Initial v1
188 sw $0, 104($8) # Initial v1
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| D | tx_thread_context_save.mip | 165 sw $3, 104($29) # Store v1
254 sw $3, 104($29) # Store v1
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| /ThreadX-v6.4.1/ports/cortex_r7/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
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| /ThreadX-v6.4.1/ports/cortex_a7/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
|
| /ThreadX-v6.4.1/ports/cortex_r5/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
|
| /ThreadX-v6.4.1/ports/cortex_a8/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
|
| /ThreadX-v6.4.1/ports/cortex_a9/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
|
| /ThreadX-v6.4.1/ports/cortex_a5/ghs/src/ |
| D | tx_thread_schedule.arm | 131 MOV v1, r0 # Save temp register in non-volatile register
133 MOV r0, v1 # Restore temp register
|
