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/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dinit_vpe1.S77 mfc0 v0, C0_MVPCTL // read C0_MVPCtl
78 or v0, (1 << 1) // set VPC
79 mtc0 v0, C0_MVPCTL // write C0_MVPCtl
87 mfc0 v0, C0_MVPCONF0 // read C0_MVPCONF0
88 ext a0_NTCS, v0, 0, 8 // extract PTC
89 ext a2_NVPES, v0, 10, 4 // extract PVPE
95 mfc0 v0, C0_VPECTL // read C0_VPECTL
96 ins v0, a3_TC, 0, 8 // insert TargTC
97 mtc0 v0, C0_VPECTL // write C0_VPECTL
105 li v0, 1 // set Halt bit
[all …]
Dinit_cp0.S63 mfc0 v0, C0_CONFIG1 // read C0_Config1
64 ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
70 mfc0 v0, C0_WATCHHI // read C0_WatchHi0
71 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
75 mfc0 v0, C0_WATCHHI, 1 // read C0_WatchHi1
76 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
80 mfc0 v0, C0_WATCHHI, 2 // read C0_WatchHi2
81 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
85 mfc0 v0, C0_WATCHHI, 3 // read C0_WatchHi3
86 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
[all …]
Dinit_caches2.S69 mfc0 v0, C0_CONFIG1 // Read C0_Config1
70 ext a3, v0, CFG1_ILSHIFT, 3 // Extract IS
105 mfc0 v0, C0_CONFIG1 // Read C0_Config1
106 ext a3, v0, CFG1_DSSHIFT, 3 // Extract DS
158 mfc0 v0, C0_CONFIG2 // Read C0_Config2
160 ext v1, v0, 4, 4 // extract L2 line size
165 ext a3, v0, 8, 4 // extrace sets per way encoding
171 ext a1, v0, 0, 4 // extract ways encoding
194 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
204 ext a3, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
[all …]
Dinit_L23caches.S123 mfc0 v0, C0_CONFIG2 // C0_Config2
126 ext v1, v0, 4, 4 // extract SL
136 ext a0, v0, 8, 4 // extract SS
142 ext a1, v0, 0, 4 // extract SA
166 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
176 ext a0, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
182 ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
Dstart.S198 lui v0, 0xbf00
200 sw v1, 1048(v0)
201 sw v1, 1056(v0)
202 sw v1, 1064(v0)
203 sw v1, 1072(v0)
204 sw v1, 1080(v0)
205 sw v1, 1088(v0)
206 sw v1, 1096(v0)
207 sw v1, 1104(v0)
Dinit_tlb.S63 mfc0 v0, C0_CONFIG1 // C0_Config1
68 ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
Dregdef.h6 #define v0 $2 /* values for function returns */ macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_vpe1.mip77 mfc0 v0, C0_MVPCTL // read C0_MVPCtl
78 or v0, (1 << 1) // set VPC
79 mtc0 v0, C0_MVPCTL // write C0_MVPCtl
87 mfc0 v0, C0_MVPCONF0 // read C0_MVPCONF0
88 ext a0_NTCS, v0, 0, 8 // extract PTC
89 ext a2_NVPES, v0, 10, 4 // extract PVPE
95 mfc0 v0, C0_VPECTL // read C0_VPECTL
96 ins v0, a3_TC, 0, 8 // insert TargTC
97 mtc0 v0, C0_VPECTL // write C0_VPECTL
105 li v0, 1 // set Halt bit
[all …]
Dinit_cp0.mip63 mfc0 v0, C0_CONFIG1 // read C0_Config1
64 ext v1, v0, 3, 1 // extract bit 3 WR (Watch registers implemented)
70 mfc0 v0, C0_WATCHHI // read C0_WatchHi0
71 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
75 mfc0 v0, C0_WATCHHI, 1 // read C0_WatchHi1
76 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
80 mfc0 v0, C0_WATCHHI, 2 // read C0_WatchHi2
81 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
85 mfc0 v0, C0_WATCHHI, 3 // read C0_WatchHi3
86 bgez v0, done_wr // Check for bit 31 (sign bit) for more Watch registers
[all …]
Dinit_caches2.mip69 mfc0 v0, C0_CONFIG1 // Read C0_Config1
70 ext a3, v0, CFG1_ILSHIFT, 3 // Extract IS
105 mfc0 v0, C0_CONFIG1 // Read C0_Config1
106 ext a3, v0, CFG1_DSSHIFT, 3 // Extract DS
158 mfc0 v0, C0_CONFIG2 // Read C0_Config2
160 ext v1, v0, 4, 4 // extract L2 line size
165 ext a3, v0, 8, 4 // extrace sets per way encoding
171 ext a1, v0, 0, 4 // extract ways encoding
194 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
204 ext a3, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
[all …]
Dregdef.h6 #define v0 $2 /* values for function returns */ macro
Dinit_L23caches.mip123 mfc0 v0, C0_CONFIG2 // C0_Config2
126 ext v1, v0, 4, 4 // extract SL
136 ext a0, v0, 8, 4 // extract SS
142 ext a1, v0, 0, 4 // extract SA
166 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
176 ext a0, v0, CFG2_TSSHIFT, 4 // Extract L3 sets per way TDS encoding
182 ext a1, v0, CFG2_TASHIFT, 4 // Extrace L3 associativity 2TA encoding
Dstart.mip198 lui v0, 0xbf00
200 sw v1, 1048(v0)
201 sw v1, 1056(v0)
202 sw v1, 1064(v0)
203 sw v1, 1072(v0)
204 sw v1, 1080(v0)
205 sw v1, 1088(v0)
206 sw v1, 1096(v0)
207 sw v1, 1104(v0)
Dinit_tlb.mip63 mfc0 v0, C0_CONFIG1 // C0_Config1
68 ext v1, v0, CFG1_MMUSSHIFT, 6 // extract MMU Size
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_context_save.S160 sw $2, 108($29) # Store v0
249 sw $2, 108($29) # Store v0
Dtx_thread_stack_build.S185 sw $0, 108($8) # Initial v0
Dtx_thread_context_restore.S161 lw $2, 108($29) # Recover v0
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/
Dtx_thread_stack_build.mip103 $2 (108) Initial v0
189 sw $0, 108($8) # Initial v0
Dtx_thread_context_save.mip166 sw $2, 108($29) # Store v0
255 sw $2, 108($29) # Store v0
Dtx_thread_context_restore.mip161 lw $2, 108($29) # Recover v0
279 lw $2, 108($29) # Recover v0
Dtx_thread_schedule.mip300 lw $2, 108($29) # Recover v0
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/
Dreadme_threadx.txt129 0x06C v0 ($2)
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/
Dreadme_threadx.txt170 0x06C v0 ($2)