| /ThreadX-v6.4.1/ports/c667x/ccs/example_build/include/ |
| D | C66XX_MACROS.hxx | 94 #define C66XX_set_core_evtset_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtset_rg_addr(i), v) argument
97 #define C66XX_set_core_evtclr_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtclr_rg_addr(i), v) argument
101 #define C66XX_set_core_evtmask_rg(i, v) C66XX_SET_RG_VALUE(C66XX_get_core_evtmask_rg_addr(i), … argument
125 #define C66XX_set_pll_pllctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, v) argument
129 #define C66XX_set_pll_pllctl_pllensrc(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PL… argument
131 #define C66XX_set_pll_pllctl_pllrst(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLL… argument
133 #define C66XX_set_pll_pllctl_pllpwrdn(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PL… argument
135 #define C66XX_set_pll_pllctl_pllen(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_PLLCTL_RG_ADDR, PLL_PLLC… argument
156 #define C66XX_set_pll_secctl_rg(v) C66XX_SET_RG_VALUE(C66XX_PLL_SECCTL_RG_ADDR, v) argument
160 #define C66XX_set_pll_secctl_bypass(v) C66XX_SET_FIELD_VALUE(C66XX_PLL_SECCTL_RG_ADDR, PLL_SEC… argument
[all …]
|
| D | TA66XX_DSP_BC_FUNCTIONS.hxx | 1210 void TA66XX_BC_write_fpga_hif_byte(uint32_t addr, uint8_t v);
1235 void TA66XX_BC_write_fpga_hif_w16(uint32_t addr, uint16_t v);
1260 void TA66XX_BC_write_fpga_hif_w32(uint32_t addr, uint32_t v);
1285 void TA66XX_BC_write_fpga_hif_w64(uint32_t addr, uint64_t v);
1553 void TA66XX_BC_write_mram_byte(uint32_t addr, uint8_t v);
1576 void TA66XX_BC_write_mram_w16(uint32_t addr, uint16_t v);
1599 void TA66XX_BC_write_mram_w32(uint32_t addr, uint32_t v);
1622 void TA66XX_BC_write_mram_w64(uint32_t addr, uint64_t v);
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/ |
| D | m32c0.h | 621 #define _m32c0_mtc0(rn, sel, v) (void) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
622 #define _m32c0_mxc0(rn, sel, v) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
628 #define _mips_mtc0(r,v) _m32c0_mtc0(r,0,v)
632 #define mips32_setconfig0(v) _mips_mtc0(C0_CONFIG,v)
633 #define mips32_xchconfig0(v) _mips_mxc0(C0_CONFIG,v)
645 #define mips32_setwatchlo(sel,v) _mips_xxc0(C0_WATCHLO + (sel)*32, ~0, v)
649 #define mips32_setwatchhi(sel,v) _mips_xxc0(C0_WATCHHI + (sel)*32, ~0, v)
653 #define mips32_setdebug(v) _mips_mtc0(C0_DEBUG,v)
654 #define mips32_xchdebug(v) _mips_mxc0(C0_DEBUG,v)
714 #define mips32_sethwrena(v) _mips_mtc0(C0_HWRENA,v)
[all …]
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | m32c0.h | 621 #define _m32c0_mtc0(rn, sel, v) (void) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
622 #define _m32c0_mxc0(rn, sel, v) _mips_xxc0 ((rn) + (sel)*32, ~0, v)
628 #define _mips_mtc0(r,v) _m32c0_mtc0(r,0,v)
632 #define mips32_setconfig0(v) _mips_mtc0(C0_CONFIG,v)
633 #define mips32_xchconfig0(v) _mips_mxc0(C0_CONFIG,v)
645 #define mips32_setwatchlo(sel,v) _mips_xxc0(C0_WATCHLO + (sel)*32, ~0, v)
649 #define mips32_setwatchhi(sel,v) _mips_xxc0(C0_WATCHHI + (sel)*32, ~0, v)
653 #define mips32_setdebug(v) _mips_mtc0(C0_DEBUG,v)
654 #define mips32_xchdebug(v) _mips_mxc0(C0_DEBUG,v)
714 #define mips32_sethwrena(v) _mips_mtc0(C0_HWRENA,v)
[all …]
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5x_smp/green/example_build/sample_threadx/ |
| D | tx_zynqmp_low_level.c | 100 static inline void CNTP_CTL_WRITE(uint32_t v) in CNTP_CTL_WRITE() argument
102 __MSR(__CNTPS_CTL_EL1, v); in CNTP_CTL_WRITE()
110 static inline void CNTP_CVAL_WRITE(uint64_t v) in CNTP_CVAL_WRITE() argument
112 __MSR(__CNTPS_CVAL_EL1, v); in CNTP_CVAL_WRITE()
|
