| /ThreadX-v6.4.1/ports/xtensa/xcc/inc/ |
| D | xtensa_rtos.h | 117 #define XT_INTS_DISABLE(reg) movi reg, PS_DI; xps reg, reg argument
118 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync argument
120 #define XT_INTS_DISABLE(reg) rsil reg, XCHAL_EXCM_LEVEL argument
121 #define XT_INTS_ENABLE(reg) wsr reg, PS; rsync argument
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| /ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/ |
| D | MP_GlobalTimer.s | 38 LDR r3, [r2, #0x208] ; Read control reg
40 STR r3, [r2, #0x208] ; Write control reg
42 ; Form control reg value
71 LDR r1, [r2, #0x208] ; Read control reg
96 LDR r1, [r0, #0x208] ; Read control reg
113 LDR r1, [r0, #0x208] ; Read control reg
|
| D | MP_PrivateTimer.s | 41 ; Form control reg value
61 LDR r1, [r0, #0x608] ; Read control reg
77 LDR r1, [r0, #0x608] ; Read control reg
|
| D | v7.S | 57 ISB ; ISB to sync the change to the CacheSizeID reg
112 ISB ; ISB to sync the change to the CacheSizeID reg
171 ISB ; ISB to sync the change to the CacheSizeID reg
225 ISB ; ISB to sync the change to the CacheSizeID reg
|
| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/ |
| D | MP_GlobalTimer.s | 38 LDR r3, [r2, #0x208] ; Read control reg
40 STR r3, [r2, #0x208] ; Write control reg
42 ; Form control reg value
71 LDR r1, [r2, #0x208] ; Read control reg
96 LDR r1, [r0, #0x208] ; Read control reg
112 LDR r1, [r0, #0x208] ; Read control reg
|
| D | MP_PrivateTimer.s | 41 ; Form control reg value
61 LDR r1, [r0, #0x608] ; Read control reg
77 LDR r1, [r0, #0x608] ; Read control reg
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/ |
| D | MP_GlobalTimer.s | 38 LDR r3, [r2, #0x208] ; Read control reg
40 STR r3, [r2, #0x208] ; Write control reg
42 ; Form control reg value
71 LDR r1, [r2, #0x208] ; Read control reg
96 LDR r1, [r0, #0x208] ; Read control reg
112 LDR r1, [r0, #0x208] ; Read control reg
|
| D | MP_PrivateTimer.s | 41 ; Form control reg value
61 LDR r1, [r0, #0x608] ; Read control reg
77 LDR r1, [r0, #0x608] ; Read control reg
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/ |
| D | m32c0.h | 583 #define _m32c0_mfc0(reg, sel) \
588 : "JK" (reg), "JK" (sel)); \
593 #define _m32c0_mtc0(reg, sel, val) \
597 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
601 #define _m32c0_mtc0(reg, sel, val) \
605 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
610 #define _m32c0_mxc0(reg, sel, val) \
613 __o = _m32c0_mfc0 (reg, sel); \
614 _m32c0_mtc0 (reg, sel, val); \
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/ |
| D | m32c0.h | 583 #define _m32c0_mfc0(reg, sel) \
588 : "JK" (reg), "JK" (sel)); \
593 #define _m32c0_mtc0(reg, sel, val) \
597 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
601 #define _m32c0_mtc0(reg, sel, val) \
605 : "dJ" ((reg32_t)(val)), "JK" (reg), "JK" (sel) \
610 #define _m32c0_mxc0(reg, sel, val) \
613 __o = _m32c0_mfc0 (reg, sel); \
614 _m32c0_mtc0 (reg, sel, val); \
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/ |
| D | tx_thread_smp_initialize_wait.S | 72 cfc1 $8, $31 # Pickup current FPU control reg
74 sw $8, ($9) # Save FPU control reg
|
| D | tx_thread_context_save.S | 113 cfc1 $8, $31 # Pickup floating point control reg
205 cfc1 $8, $31 # Pickup floating point control reg
|
| /ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/src/ |
| D | tx_thread_smp_initialize_wait.mip | 72 cfc1 $8, $31 # Pickup current FPU control reg
74 sw $8, ($9) # Save FPU control reg
|
| /ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/ |
| D | crti.s | 3 .option %reg
|
| /ThreadX-v6.4.1/ports/cortex_m4/ghs/inc/ |
| D | tx_port.h | 353 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_m3/ghs/inc/ |
| D | tx_port.h | 353 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_m7/ghs/inc/ |
| D | tx_port.h | 353 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_r4/ghs/inc/ |
| D | tx_port.h | 358 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_r7/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_a8/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports_arch/ARMv7-M/threadx/ghs/inc/ |
| D | tx_port.h | 369 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_a9/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_r5/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_a5/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
| /ThreadX-v6.4.1/ports/cortex_a7/ghs/inc/ |
| D | tx_port.h | 361 %reg a in restore_ints()
|
