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/ThreadX-v6.4.1/ports/arc_em/metaware/src/
Dtx_thread_stack_build.s142 mov r5, 0 ; Build initial clear value
143 st r5, [r3, 4] ; Store initial LP_START
144 st r5, [r3, 8] ; Store initial LP_END
145 st r5, [r3, 12] ; Store initial LP_COUNT
146 st r5, [r3, 16] ; Store initial blink
148 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
150 st r5, [r3, 32] ; Store initial r25
151 st r5, [r3, 36] ; Store initial r24
152 st r5, [r3, 40] ; Store initial r23
153 st r5, [r3, 44] ; Store initial r22
[all …]
/ThreadX-v6.4.1/ports/arc_hs/metaware/src/
Dtx_thread_stack_build.s142 mov r5, 0 ; Build initial clear value
143 st r5, [r3, 4] ; Store initial LP_START
144 st r5, [r3, 8] ; Store initial LP_END
145 st r5, [r3, 12] ; Store initial LP_COUNT
146 st r5, [r3, 16] ; Store initial blink
148 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
150 st r5, [r3, 32] ; Store initial r25
151 st r5, [r3, 36] ; Store initial r24
152 st r5, [r3, 40] ; Store initial r23
153 st r5, [r3, 44] ; Store initial r22
[all …]
Dtx_thread_register_bank_assign.s89 ld r5, [r4, 164] ; Pickup initial status32 from stack area
90 …or r5, r5, r2 ; Modify initial status32 with register bank n…
91 st r5, [r4, 164] ; Store initial status32 in stack area
104 mov r5, 3 ; Build type for hardware interrupt context
106 st r5, [r4, 0] ; Set stack frame type
/ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/src/
Dtx_thread_stack_build.s146 mov r5, 0 ; Build initial clear value
147 st r5, [r3, 4] ; Store initial LP_START
148 st r5, [r3, 8] ; Store initial LP_END
149 st r5, [r3, 12] ; Store initial LP_COUNT
150 st r5, [r3, 16] ; Store initial blink
152 st r5, [r3, 24] ; Store initial fp (0 for backtrace)
154 st r5, [r3, 32] ; Store initial r25
155 st r5, [r3, 36] ; Store initial r24
156 st r5, [r3, 40] ; Store initial r23
157 st r5, [r3, 44] ; Store initial r22
[all …]
Dtx_thread_schedule.s139 llock r5, [r0]
140 breq r5, 0, _continue
143 add r5, r1, 1
144 scond r5, [r0]
159 …ld r5, [r0, 164] ; Pickup the ready bit for this thread to see …
160 breq r5, 0, _tx_thread_schedule_restart ; If not set, start over
185 ld r5, [r0, 24] ; Pickup time-slice for this thread
194 st r5, [r6] ; Setup time-slice
/ThreadX-v6.4.1/ports/cortex_r5/ac5/example_build/
Dbuild_threadx.bat2 armasm -g --cpu=cortex-r5 --apcs=interwork tx_initialize_low_level.s
3 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_stack_build.s
4 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_schedule.s
5 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_system_return.s
6 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_save.s
7 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_context_restore.s
8 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_interrupt_control.s
9 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_timer_interrupt.s
10 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_restore.s
11 armasm -g --cpu=cortex-r5 --apcs=interwork ../src/tx_thread_fiq_context_save.s
[all …]
/ThreadX-v6.4.1/ports/cortex_r5/gnu/example_build/
Dbuild_threadx.bat2 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
3 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_stack_build.S
4 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_schedule.S
5 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_system_return.S
6 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_save.S
7 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_context_restore.S
8 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_control.S
9 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_timer_interrupt.S
10 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_disable.S
11 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 ../src/tx_thread_interrupt_restore.S
[all …]
Dbuild_threadx_sample.bat1 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 reset.S
2 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 crt0.S
3 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 tx_initialize_low_level.S
4 arm-none-eabi-gcc -c -g -mcpu=cortex-r5 -I../../../../common/inc -I../inc sample_threadx.c
5 arm-none-eabi-ld -A cortex-r5 -T sample_threadx.ld reset.o crt0.o tx_initialize_low_level.o sample_…
/ThreadX-v6.4.1/ports/cortex_m23/ac6/src/
Dtx_thread_schedule.S152 MOV r5, r9
158 MOV r5, lr // Copy lr to saveable register
159 STR r5, [r3] // Save lr on the stack
164 LDR r5, =0x90 // Secure stack index offset
165 LDR r5, [r1, r5] // Load secure stack index
166 CBZ r5, _skip_secure_save // Skip save if there is no secure context
177 LDR r5, [r4] // Pickup current time-slice
178 CBZ r5, __tx_ts_new // If not active, skip processing
182 STR r5, [r1, #24] // Save current time-slice
186 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.4.1/ports/cortex_m23/iar/src/
Dtx_thread_schedule.s147 MOV r5, r9
153 MOV r5, lr // Copy lr to saveable register
154 STR r5, [r3] // Save lr on the stack
159 LDR r5, =0x90 // Secure stack index offset
160 LDR r5, [r1, r5] // Load secure stack index
161 CBZ r5, _skip_secure_save // Skip save if there is no secure context
172 LDR r5, [r4] // Pickup current time-slice
173 CBZ r5, __tx_ts_new // If not active, skip processing
177 STR r5, [r1, #24] // Save current time-slice
181 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.4.1/ports/cortex_m23/gnu/src/
Dtx_thread_schedule.S148 MOV r5, r9
154 MOV r5, lr // Copy lr to saveable register
155 STR r5, [r3] // Save lr on the stack
160 LDR r5, =0x90 // Secure stack index offset
161 LDR r5, [r1, r5] // Load secure stack index
162 CBZ r5, _skip_secure_save // Skip save if there is no secure context
173 LDR r5, [r4] // Pickup current time-slice
174 CBZ r5, __tx_ts_new // If not active, skip processing
178 STR r5, [r1, #24] // Save current time-slice
182 MOVW r5, #0 // Build clear value
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m23/gnu/module_manager/src/
Dtx_thread_schedule.S152 STR r5, [r2, #52] // Save r5
251 MOV r5, r9
257 MOV r5, lr // Copy lr to saveable register
258 STR r5, [r3] // Save lr on the stack
263 LDR r5, =0xC4 // Secure stack index offset
264 LDR r5, [r1, r5] // Load secure stack index
265 CBZ r5, _skip_secure_save // Skip save if there is no secure context
276 LDR r5, [r4] // Pickup current time-slice
277 CBZ r5, __tx_ts_new // If not active, skip processing
281 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m23/ac6/module_manager/src/
Dtx_thread_schedule.S156 STR r5, [r2, #52] // Save r5
255 MOV r5, r9
261 MOV r5, lr // Copy lr to saveable register
262 STR r5, [r3] // Save lr on the stack
267 LDR r5, =0xC4 // Secure stack index offset
268 LDR r5, [r1, r5] // Load secure stack index
269 CBZ r5, _skip_secure_save // Skip save if there is no secure context
280 LDR r5, [r4] // Pickup current time-slice
281 CBZ r5, __tx_ts_new // If not active, skip processing
285 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m23/iar/module_manager/src/
Dtx_thread_schedule.s160 STR r5, [r2, #52] // Save r5
252 MOV r5, r9
258 MOV r5, lr // Copy lr to saveable register
259 STR r5, [r3] // Save lr on the stack
264 LDR r5, =0xC4 // Secure stack index offset
265 LDR r5, [r1, r5] // Load secure stack index
266 CBZ r5, _skip_secure_save // Skip save if there is no secure context
277 LDR r5, [r4] // Pickup current time-slice
278 CBZ r5, __tx_ts_new // If not active, skip processing
282 STR r5, [r1, #24] // Save current time-slice
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m0+/ac6/module_manager/src/
Dtx_thread_schedule.S144 STR r5, [r2, #52] // Save r5
237 MOV r5, r9 // Pick up r9
243 MOV r5, lr // Move lr into r5
244 STR r5, [r3] // Save lr
250 LDR r5, [r4] // Pickup current time-slice
251 CMP r5, #0
256 STR r5, [r1, #24] // Save current time-slice
324 LDR r5, [r1, #24] // Pickup thread's current time-slice
330 STR r5, [r4] // Setup global time-slice
344 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m0+/gnu/module_manager/src/
Dtx_thread_schedule.S144 STR r5, [r2, #52] // Save r5
237 MOV r5, r9 // Pick up r9
243 MOV r5, lr // Move lr into r5
244 STR r5, [r3] // Save lr
250 LDR r5, [r4] // Pickup current time-slice
251 CMP r5, #0
256 STR r5, [r1, #24] // Save current time-slice
324 LDR r5, [r1, #24] // Pickup thread's current time-slice
330 STR r5, [r4] // Setup global time-slice
344 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.4.1/ports_module/cortex_m0+/iar/module_manager/src/
Dtx_thread_schedule.S136 STR r5, [r2, #52] // Save r5
222 MOV r5, r9 // Pick up r9
228 MOV r5, lr // Move lr into r5
229 STR r5, [r3] // Save lr
235 LDR r5, [r4] // Pickup current time-slice
236 CMP r5, #0
241 STR r5, [r1, #24] // Save current time-slice
309 LDR r5, [r1, #24] // Pickup thread's current time-slice
315 STR r5, [r4] // Setup global time-slice
329 MRS r5, CONTROL // Pickup current CONTROL register
[all …]
/ThreadX-v6.4.1/ports/cortex_m0/ac5/src/
Dtx_thread_schedule.s170 LDR r5, [r4] ; Pickup current time-slice
171 CMP r5, #0 ; If not active, skip processing
176 STR r5, [r1, #24] ; Save current time-slice
180 MOVS r5, #0 ; Build clear value
181 STR r5, [r4] ; Clear time-slice
204 LDR r5, [r1, #24] ; Pickup thread's current time-slice
210 STR r5, [r4] ; Setup global time-slice
230 MOV r9,r5 ;
/ThreadX-v6.4.1/ports/cortex_m0/ac6/src/
Dtx_thread_schedule.S183 LDR r5, [r4] @ Pickup current time-slice
184 CMP r5, #0 @ If not active, skip processing
189 STR r5, [r1, #24] @ Save current time-slice
193 MOVS r5, #0 @ Build clear value
194 STR r5, [r4] @ Clear time-slice
217 LDR r5, [r1, #24] @ Pickup thread's current time-slice
223 STR r5, [r4] @ Setup global time-slice
243 MOV r9,r5 @
/ThreadX-v6.4.1/ports/cortex_m0/gnu/src/
Dtx_thread_schedule.S183 LDR r5, [r4] @ Pickup current time-slice
184 CMP r5, #0 @ If not active, skip processing
189 STR r5, [r1, #24] @ Save current time-slice
193 MOVS r5, #0 @ Build clear value
194 STR r5, [r4] @ Clear time-slice
217 LDR r5, [r1, #24] @ Pickup thread's current time-slice
223 STR r5, [r4] @ Setup global time-slice
243 MOV r9,r5 @
/ThreadX-v6.4.1/ports/cortex_m0/iar/src/
Dtx_thread_schedule.s167 LDR r5, [r4] ; Pickup current time-slice
168 CMP r5, #0 ; If not active, skip processing
173 STR r5, [r1, #24] ; Save current time-slice
177 MOVS r5, #0 ; Build clear value
178 STR r5, [r4] ; Clear time-slice
202 LDR r5, [r1, #24] ; Pickup thread's current time-slice
208 STR r5, [r4] ; Setup global time-slice
228 MOV r9,r5 ;
/ThreadX-v6.4.1/ports/cortex_m0/keil/src/
Dtx_thread_schedule.s170 LDR r5, [r4] ; Pickup current time-slice
171 CMP r5, #0 ; If not active, skip processing
176 STR r5, [r1, #24] ; Save current time-slice
180 MOVS r5, #0 ; Build clear value
181 STR r5, [r4] ; Clear time-slice
205 LDR r5, [r1, #24] ; Pickup thread's current time-slice
211 STR r5, [r4] ; Setup global time-slice
231 MOV r9,r5 ;
/ThreadX-v6.4.1/ports/cortex_a9/gnu/src/
Dtx_thread_schedule.S149 MOV r5, r0 // Save r0
151 MOV r0, r5 // Restore r0
156 POP {r4, r5} // Pickup the stack type and saved CPSR
161 MSR SPSR_cxsf, r5 // Setup SPSR for return
164 MSR SPSR_cxsf, r5 // Setup SPSR for return
203 MSR CPSR_cxsf, r5 // Recover CPSR
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_schedule.S149 MOV r5, r0 // Save r0
151 MOV r0, r5 // Restore r0
156 POP {r4, r5} // Pickup the stack type and saved CPSR
161 MSR SPSR_cxsf, r5 // Setup SPSR for return
164 MSR SPSR_cxsf, r5 // Setup SPSR for return
203 MSR CPSR_cxsf, r5 // Recover CPSR
/ThreadX-v6.4.1/ports/cortex_a9/ac6/src/
Dtx_thread_schedule.S149 MOV r5, r0 // Save r0
151 MOV r0, r5 // Restore r0
156 POP {r4, r5} // Pickup the stack type and saved CPSR
161 MSR SPSR_cxsf, r5 // Setup SPSR for return
164 MSR SPSR_cxsf, r5 // Setup SPSR for return
203 MSR CPSR_cxsf, r5 // Recover CPSR

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