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/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
DMP_GlobalTimer.s76 STR r1, [r2, #0x210] ; Write lower 32 bits
77 STR r0, [r2, #0x214] ; Write upper 32 bits
125 ; r0: Address of unsigned int for bits 63:32
126 ; r1: Address of unsigned int for bits 31:0
132 LDR r12,[r2, #0x04] ; Read bits 63:32
133 LDR r3, [r2, #0x00] ; Read bits 31:0
134 LDR r2, [r2, #0x04] ; Re-read bits 63:32
136 CMP r2, r12 ; Have the top bits changed?
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
DMP_GlobalTimer.s76 STR r1, [r2, #0x210] ; Write lower 32 bits
77 STR r0, [r2, #0x214] ; Write upper 32 bits
124 ; r0: Address of unsigned int for bits 63:32
125 ; r1: Address of unsigned int for bits 31:0
131 LDR r12,[r2, #0x04] ; Read bits 63:32
132 LDR r3, [r2, #0x00] ; Read bits 31:0
133 LDR r2, [r2, #0x04] ; Re-read bits 63:32
135 CMP r2, r12 ; Have the top bits changed?
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
DMP_GlobalTimer.s76 STR r1, [r2, #0x210] ; Write lower 32 bits
77 STR r0, [r2, #0x214] ; Write upper 32 bits
124 ; r0: Address of unsigned int for bits 63:32
125 ; r1: Address of unsigned int for bits 31:0
131 LDR r12,[r2, #0x04] ; Read bits 63:32
132 LDR r3, [r2, #0x00] ; Read bits 31:0
133 LDR r2, [r2, #0x04] ; Re-read bits 63:32
135 CMP r2, r12 ; Have the top bits changed?
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/src/
Dtx_thread_interrupt_control.S81 and $8, $8, $9 # Isolate interrupt lockout bits
82 or $8, $8, $4 # Put new lockout bits in
/ThreadX-v6.4.1/ports/risc-v32/iar/src/
Dtx_thread_interrupt_control.s86 and t0, t0, t2 ; Isolate interrupt lockout bits
87 or t0, t0, a0 ; Put new lockout bits in
/ThreadX-v6.4.1/ports/cortex_a9/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/arm11/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/arm9/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/cortex_a15/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/cortex_a8/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/cortex_a5/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports/cortex_a7/iar/example_build/
Dcstartup.s98 ; Mode, correspords to bits 0-5 in CPSR
100 MODE_MSK DEFINE 0x1F ; Bit mask for mode bits in CPSR
115 BIC r0, r0, #MODE_MSK ; Clear the mode bits
116 ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
122 BIC r0, r0, #MODE_MSK ; Clear the mode bits
123 ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
129 BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
130 ORR r0 ,r0, #SYS_MODE ; Set System mode bits
/ThreadX-v6.4.1/ports_module/cortex_r4/iar/module_manager/src/
Dtx_thread_interrupt_control.s75 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
76 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_r5/iar/src/
Dtx_thread_interrupt_control.s83 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
84 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_r4/iar/src/
Dtx_thread_interrupt_control.s83 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
84 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_a15/iar/src/
Dtx_thread_interrupt_control.s82 AND r1, r3, r2 ; Clear interrupt lockout bits
83 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_interrupt_control.s86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
87 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_interrupt_control.S88 BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits
89 ORR r1, r1, r0 @ Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/src/
Dtx_thread_interrupt_control.S88 BIC r1, r3, #INT_MASK @ Clear interrupt lockout bits
89 ORR r1, r1, r0 @ Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_interrupt_control.s86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
87 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_interrupt_control.s86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
87 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_interrupt_control.s86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
87 ORR r1, r1, r0 ; Or-in new interrupt lockout bits
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_interrupt_control.s86 BIC r1, r3, #INT_MASK ; Clear interrupt lockout bits
87 ORR r1, r1, r0 ; Or-in new interrupt lockout bits

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