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Searched refs:SR_HINT5 (Results 1 – 2 of 2) sorted by relevance

/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dm32c0.h158 #define SR_HINT5 0x00008000 /* enable h/w interrupt 6 */ macro
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dm32c0.h158 #define SR_HINT5 0x00008000 /* enable h/w interrupt 6 */ macro