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Searched refs:MPIDR_CPUID_CPU0 (Results 1 – 15 of 15) sorted by relevance

/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
Dv7.h89 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
Dv7.h89 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/example_build/
Dv7.h92 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a9/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/ports/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a12/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a7/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a8/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a15/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a7_smp/ac5/example_build/sample_threadx/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a5/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports/cortex_a17/gnu/example_build/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro
/ThreadX-v6.4.1/ports_smp/cortex_a5_smp/ac5/example_build/sample_threadx/
Dv7.h102 #define MPIDR_CPUID_CPU0 0x0 macro