| /ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/ |
| D | tx_thread_irq_nesting_end.s | 26 DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts
28 DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts
31 IRQ_MODE_BITS EQU 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_c, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 33 DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts
35 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
103 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
104 MSR CPSR_c, r0 @ Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a9/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a5/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports_smp/cortex_a5_smp/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 33 DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts
35 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
103 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
104 MSR CPSR_c, r0 @ Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/arm11/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 26 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
28 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
31 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 @ Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/arm11/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_r5/ac6/src/ |
| D | tx_thread_irq_nesting_end.S | 33 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
35 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
106 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
107 MSR CPSR_c, r0 @ Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/arm9/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a7/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports_smp/cortex_a7_smp/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 33 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
35 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
106 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
107 MSR CPSR_c, r0 @ Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/arm9/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 26 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
28 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
31 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 @ Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_r4/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 26 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
28 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
31 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
99 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
100 MSR CPSR_c, r0 @ Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_r5/gnu/src/ |
| D | tx_thread_irq_nesting_end.S | 26 DISABLE_INTS = 0xC0 @ Disable IRQ/FIQ interrupts
28 DISABLE_INTS = 0x80 @ Disable IRQ interrupts
31 IRQ_MODE_BITS = 0x12 @ IRQ mode bits
99 ORR r0, r0, #IRQ_MODE_BITS @ Build IRQ mode CPSR
100 MSR CPSR_c, r0 @ Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a8/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
39 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_cxsf, r0 ; Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports_smp/arc_hs_smp/metaware/example_build/sample_threadx/ |
| D | vectors.s | 24 .long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64
25 .long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68
26 .long _tx_undefined_0 ; IRQ 18 offset 0x48 72
27 .long _tx_smp_inter_core ; IRQ 19 offset 0x4C 76
28 .long _tx_undefined_2 ; IRQ 20 offset 0x50 80
|
| /ThreadX-v6.4.1/ports/arc_hs/metaware/example_build/sample_threadx/ |
| D | vectors.s | 24 .long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64
25 .long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68
26 .long _tx_undefined_0 ; IRQ 18 offset 0x48 72
27 .long _tx_undefined_1 ; IRQ 19 offset 0x4C 76
28 .long _tx_undefined_2 ; IRQ 20 offset 0x50 80
|
| /ThreadX-v6.4.1/ports/cortex_a15/iar/src/ |
| D | tx_thread_irq_nesting_end.s | 33 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ/FIQ interrupts
35 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts
38 IRQ_MODE_BITS DEFINE 0x12 ; IRQ mode bits
102 ORR r0, r0, #IRQ_MODE_BITS ; Build IRQ mode CPSR
103 MSR CPSR_c, r0 ; Reenter IRQ mode
|
| /ThreadX-v6.4.1/ports/arc_em/metaware/example_build/sample_threadx/ |
| D | vectors.s | 24 .long _tx_timer_0 ; IRQ 16 Timer 0 offset 0x40 64
25 .long _tx_timer_1 ; IRQ 17 Timer 1 offset 0x44 68
26 .long _tx_undefined_0 ; IRQ 18 offset 0x48 72
27 .long _tx_undefined_1 ; IRQ 19 offset 0x4C 76
28 .long _tx_undefined_2 ; IRQ 20 offset 0x50 80
|
| /ThreadX-v6.4.1/ports/cortex_r7/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a9/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a7/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_r4/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a8/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
| /ThreadX-v6.4.1/ports/cortex_a5/ghs/src/ |
| D | tx_thread_irq_nesting_end.arm | 33 DISABLE_INTS = 0xC0 # Disable IRQ and FIQ interrupts
35 DISABLE_INTS = 0x80 # Disable IRQ interrupts
38 IRQ_MODE_BITS = 0x12 # IRQ mode bits
54 /* This function is called by the application from IRQ mode after */
55 /* _tx_thread_irq_nesting_start has been called and switches the IRQ */
56 /* processing from system mode back to IRQ mode prior to the ISR */
64 /* This function returns with IRQ interrupts disabled. */
100 ORR r0, r0, IRQ_MODE_BITS # Build IRQ mode CPSR
101 MSR CPSR_c, r0 # Re-enter IRQ mode
|
