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Searched refs:FIQ_MODE_BITS (Results 1 – 25 of 45) sorted by relevance

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/ThreadX-v6.4.1/ports/cortex_a9/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_fiq_nesting_end.s35 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
104 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a9/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a15/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a17/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a17/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a12/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a12/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a15/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports_arch/ARMv7-A/threadx/common/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a5/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a8/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a8/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a7/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a5/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a7/gnu/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 // FIQ mode bits define
110 ORR r0, r0, #FIQ_MODE_BITS // Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_fiq_nesting_end.s38 FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits label
101 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_fiq_nesting_end.s38 FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits label
101 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_r5/ac6/src/
Dtx_thread_fiq_nesting_end.S38 FIQ_MODE_BITS = 0x11 @ FIQ mode bits define
106 ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_fiq_nesting_end.s38 FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits label
101 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/arm9/gnu/src/
Dtx_thread_fiq_nesting_end.S31 FIQ_MODE_BITS = 0x11 @ FIQ mode bits define
102 ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_fiq_nesting_end.s38 FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits label
101 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/arm11/gnu/src/
Dtx_thread_fiq_nesting_end.S31 FIQ_MODE_BITS = 0x11 @ FIQ mode bits define
102 ORR r0, r0, #FIQ_MODE_BITS @ Build IRQ mode CPSR
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/
Dtx_thread_fiq_nesting_end.s28 FIQ_MODE_BITS EQU 0x11 ; FIQ mode bits define
97 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_fiq_nesting_end.s38 FIQ_MODE_BITS DEFINE 0x11 ; FIQ mode bits label
101 ORR r0, r0, #FIQ_MODE_BITS ; Build IRQ mode CPSR

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