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/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_L23caches.mip60 // Use CCA Override disable the L2 cache or initialize the L2
61 // and L3 caches if CCA override is not available.
66 // the l2 CCA override is not present and the L2 will have to be initialized
71 // Diaable the L2 cache using CCA override by writting a 0x50 to
72 // the GCR Base register. 0x50 enables the CCA override bit and sets
73 // the CCA to uncached.
76 li a3, 0x50 // Enable CCA and set to uncached
81 // of the CCA override took. If it did skip the L2 and L3
87 bnez a0, done_l23 // Skip uncached execution if CCA
91 // If the code gets here the CCA override is not available so
[all …]
Dinit_caches2.mip133 // Use CCA Override disable the L2 cache
136 // Disable the L2 cache using CCA override by writing a 0x50 to
137 // the GCR Base register. 0x50 enables the CCA override bit and sets
138 // the CCA to uncached.
141 li a3, 0x50 // Enable CCA and set to uncached
228 // disable CCA Override to enable L2 cache
230 ins a0, zero, 0, 8 // CCA Override disabled
240 // Set CCA for kseg0 to cacheable
243 li v1, 3 // CCA for non coherent core
244 li v1, 5 // CCA for coherent cores
Dcps.h145 #define CCA 15 macro
Dinit_vpe1.mip220 // and the L2$ has been initialized or "disabled" via CCA override.
/ThreadX-v6.4.1/ports_smp/mips32_interaptiv_smp/gnu/example_build/
Dcps.h145 #define CCA 15 macro