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/ThreadX-v6.3.0/test/smp/cmake/regression/
Dgenerate_test_file.sh6 line=`sed -n '/_tx_linux_timer_interrupt/=' $src | tail -n 1`
7 sed "${line}iVOID test_interrupt_dispatch(VOID);" $src > tmp1
8 line=`sed -n '/_tx_timer_interrupt/=' $src | tail -n 1`
9 sed "${line}itest_interrupt_dispatch();" tmp1 > $dst
/ThreadX-v6.3.0/test/tx/cmake/regression/
Dgenerate_test_file.sh6 line=`sed -n '/_tx_linux_timer_interrupt/=' $src | tail -n 1`
7 sed "${line}iVOID test_interrupt_dispatch(VOID);" $src > tmp1
8 line=`sed -n '/_tx_timer_interrupt/=' $src | tail -n 1`
9 sed "${line}itest_interrupt_dispatch();" tmp1 > $dst
/ThreadX-v6.3.0/ports_smp/mips32_interaptiv_smp/green/example_build/
Dinit_caches2.mip67 // v1 set to line size, will be used to increment through the cache tags
84 add a2, v1 // Increment line address by line size
103 // v1 set to line size, will be used to increment through the cache tags
120 add a2, v1 // Increment line address by line size
160 ext v1, v0, 4, 4 // extract L2 line size
162 sllv v1, a2, v1 // Now have true L2$ line size in bytes
189 add a2, v1 // Get next line address (each tag covers one line)
194 ext v1, v0, CFG2_TLSHIFT, 4 // Extract L3 line size
201 sllv v1, a2, v1 // Decode L3$ line size in bytes
225 add a2, v1 // Get next line address
/ThreadX-v6.3.0/test/ports/
Dazrtos_test_tx_iar_cortex_m4.bat5 @REM Read about available command line parameters in the C-SPY Debugging
6 @REM Guide. Hints about additional command line parameters that may be
/ThreadX-v6.3.0/ports/win32/vs_2019/src/
Dtx_initialize_low_level.c100 void _tx_win32_debug_entry_insert(char *action, char *file, unsigned long line) in _tx_win32_debug_entry_insert() argument
111 …in32_debug_entry_array[_tx_win32_debug_entry_index].tx_win32_debug_entry_line = line; in _tx_win32_debug_entry_insert()
/ThreadX-v6.3.0/ports/cortex_m55/ac6/example_build/
DCS300_ac6.sct2 ; command above MUST be in first line (no comment above!)
4 ;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
DCS300_ac6_s.sct2 ; command above MUST be in first line (no comment above!)
4 ;Note: Add '-mcmse' to first line if your software model is "Secure Mode".
/ThreadX-v6.3.0/ports_smp/cortex_a9_smp/ac5/example_build/sample_threadx/
Dv7.s59 AND r2, r1, #&7 ; extract the line length field
60 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
114 AND r2, r1, #&7 ; extract the line length field
115 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
173 AND r2, r1, #&7 ; extract the line length field
174 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
227 AND r2, r1, #&7 ; extract the line length field
228 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
/ThreadX-v6.3.0/ports_smp/cortex_r8_smp/ac5/example_build/sample_threadx/
Dv7.S59 AND r2, r1, #&7 ; extract the line length field
60 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
114 AND r2, r1, #&7 ; extract the line length field
115 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
173 AND r2, r1, #&7 ; extract the line length field
174 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
227 AND r2, r1, #&7 ; extract the line length field
228 ADD r2, r2, #4 ; add 4 for the line length offset (log2 16 bytes)
/ThreadX-v6.3.0/ports/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/
DARMCM23_ac6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
DARMCM33_AC6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports_module/cortex_m33/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
DARMCM33_AC6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/
DARMCM23_ac6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
DARMCM33_AC6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports_module/cortex_m23/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM23_TZ/
DARMCM23_ac6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports_module/cortex_m23/ac6/example_build/demo_threadx_non-secure_zone/RTE/Device/ARMCM23_TZ/
DARMCM23_ac6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports_module/cortex_m33/ac6/example_build/demo_secure_zone/RTE/Device/ARMCM33_DSP_FP_TZ/
DARMCM33_AC6.sct2 ; command above MUST be in first line (no comment above!)
/ThreadX-v6.3.0/ports/cortex_a76/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports/cortex_a76ae/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports/cortex_a77/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports/linux/gnu/src/
Dtx_initialize_low_level.c112 void _tx_linux_debug_entry_insert(char *action, char *file, unsigned long line) in _tx_linux_debug_entry_insert() argument
130 …inux_debug_entry_array[_tx_linux_debug_entry_index].tx_linux_debug_entry_line = line; in _tx_linux_debug_entry_insert()
/ThreadX-v6.3.0/ports_module/cortex_a35/ac6/example_build/sample_threadx_module_manager/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports/cortex_a75/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports_module/cortex_a35/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary
/ThreadX-v6.3.0/ports/cortex_a72/ac6/example_build/sample_threadx/
Dsample_threadx.scat19 ; All stacks and heap are aligned to a cache-line boundary
31 ; All stacks and heap are aligned to a cache-line boundary

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