Home
last modified time | relevance | path

Searched refs:ENABLE_INTS (Results 1 – 20 of 20) sorted by relevance

/ThreadX-v6.2.1/ports/arm9/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
99 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/arm11/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
99 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/arm9/ac5/src/
Dtx_thread_schedule.s35 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
37 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
100 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/arm11/ac5/src/
Dtx_thread_schedule.s35 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
37 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
100 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/arm11/gnu/src/
Dtx_thread_schedule.S27 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
29 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
112 BIC r0, r2, #ENABLE_INTS @ Clear the disable bit(s)
/ThreadX-v6.2.1/ports/arm9/gnu/src/
Dtx_thread_schedule.S27 ENABLE_INTS = 0xC0 @ IRQ & FIQ Interrupts enabled mask define
29 ENABLE_INTS = 0x80 @ IRQ Interrupts enabled mask define
112 BIC r0, r2, #ENABLE_INTS @ Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a7/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
102 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a5/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
102 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_r4/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a9/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
102 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a8/iar/src/
Dtx_thread_schedule.s34 ENABLE_INTS DEFINE 0xC0 ; IRQ & FIQ Interrupts enabled mask label
36 ENABLE_INTS DEFINE 0x80 ; IRQ Interrupts enabled mask label
102 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_schedule.s36 #define ENABLE_INTS 0xC0 // IRQ & FIQ Interrupts enabled mask macro
38 #define ENABLE_INTS 0x80 // IRQ Interrupts enabled mask macro
258 BIC r0, r2, #ENABLE_INTS // Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_r5/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_r7/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a5/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a7/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a8/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports/cortex_a9/ghs/src/
Dtx_thread_schedule.arm34 ENABLE_INTS = 0xC0 # IRQ & FIQ Interrupts enabled mask
36 ENABLE_INTS = 0x80 # IRQ Interrupts enabled mask
91 BIC r0, r2, ENABLE_INTS # Clear the disable bit(s)
/ThreadX-v6.2.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_schedule.s47 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
49 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define
270 BIC r0, r2, #ENABLE_INTS ; Clear the disable bit(s)
/ThreadX-v6.2.1/ports_module/cortex_a7/iar/module_manager/src/
Dtx_thread_schedule.s37 ENABLE_INTS EQU 0xC0 ; IRQ & FIQ Interrupts enabled mask define
39 ENABLE_INTS EQU 0x80 ; IRQ Interrupts enabled mask define