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Searched defs:DISABLE_INTS (Results 1 – 25 of 167) sorted by relevance

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/ThreadX-v6.4.1/ports/arm9/ac5/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled define
34 DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled define
Dtx_thread_system_return.s33 DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled define
35 DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled define
/ThreadX-v6.4.1/ports/arm11/ac5/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled define
34 DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled define
Dtx_thread_system_return.s33 DISABLE_INTS EQU 0xC0 ; IRQ & FIQ interrupts disabled define
35 DISABLE_INTS EQU 0x80 ; IRQ interrupts disabled define
/ThreadX-v6.4.1/ports/cortex_a9/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
Dtx_thread_context_save.s34 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
36 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
Dtx_thread_fiq_nesting_end.s33 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts label
35 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts label
Dtx_thread_irq_nesting_end.s34 DISABLE_INTS DEFINE 0xC0 ; Disable IRQ & FIQ interrupts label
36 DISABLE_INTS DEFINE 0x80 ; Disable IRQ interrupts label
/ThreadX-v6.4.1/ports/cortex_a5/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
/ThreadX-v6.4.1/ports/arm9/gnu/src/
Dtx_thread_interrupt_disable.S26 DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled define
28 DISABLE_INTS = 0x80 @ IRQ interrupts disabled define
/ThreadX-v6.4.1/ports/arm9/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
/ThreadX-v6.4.1/ports/arm11/gnu/src/
Dtx_thread_interrupt_disable.S26 DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled define
28 DISABLE_INTS = 0x80 @ IRQ interrupts disabled define
/ThreadX-v6.4.1/ports/arm11/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
/ThreadX-v6.4.1/ports/cortex_a7/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
/ThreadX-v6.4.1/ports/cortex_a8/iar/src/
Dtx_thread_interrupt_disable.s32 DISABLE_INTS DEFINE 0xC0 ; IRQ & FIQ interrupts disabled label
34 DISABLE_INTS DEFINE 0x80 ; IRQ interrupts disabled label
/ThreadX-v6.4.1/ports_module/cortex_a7/gnu/module_manager/src/
Dtx_thread_fiq_nesting_end.s30 DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts define
32 DISABLE_INTS = 0x80 // Disable IRQ interrupts define
Dtx_thread_irq_nesting_end.s30 DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts define
32 DISABLE_INTS = 0x80 // Disable IRQ interrupts define
/ThreadX-v6.4.1/ports_module/cortex_a7/iar/module_manager/src/
Dtx_thread_fiq_nesting_end.s23 DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts define
25 DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts define
Dtx_thread_irq_nesting_end.s26 DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts define
28 DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts define
/ThreadX-v6.4.1/ports_module/cortex_a7/ac5/module_manager/src/
Dtx_thread_fiq_nesting_end.s33 DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts define
35 DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts define
Dtx_thread_irq_nesting_end.s33 DISABLE_INTS EQU 0xC0 ; Disable IRQ & FIQ interrupts define
35 DISABLE_INTS EQU 0x80 ; Disable IRQ interrupts define
/ThreadX-v6.4.1/ports_smp/cortex_a9_smp/gnu/src/
Dtx_thread_irq_nesting_end.S33 DISABLE_INTS = 0xC0 @ Disable IRQ & FIQ interrupts define
35 DISABLE_INTS = 0x80 @ Disable IRQ interrupts define
/ThreadX-v6.4.1/ports/cortex_a9/gnu/src/
Dtx_thread_fiq_nesting_end.S33 DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts define
35 DISABLE_INTS = 0x80 // Disable IRQ interrupts define
Dtx_thread_irq_nesting_end.S33 DISABLE_INTS = 0xC0 // Disable IRQ/FIQ interrupts define
35 DISABLE_INTS = 0x80 // Disable IRQ interrupts define
/ThreadX-v6.4.1/ports_smp/cortex_r8_smp/ac5/src/
Dtx_thread_irq_nesting_end.s22 DISABLE_INTS EQU 0xC0 // Disable IRQ & FIQ interrupts define
24 DISABLE_INTS EQU 0x80 // Disable IRQ interrupts define

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