1*** Variables ***
2${UART}                             sysbus.mmuart1
3${URI}                              @https://dl.antmicro.com/projects/renode
4${PLATFORM}                         @platforms/cpus/polarfire-soc.repl
5${VARIABLE_ADDRESS_CPU1}            0x81000000
6${VARIABLE_ADDRESS_CPU2}            0x81000100
7
8# Registers used
9${a0}                               10
10${a1}                               11
11${a2}                               12
12${a3}                               13
13
14*** Keywords ***
15Create Machine
16    Execute Command                 mach create
17    Execute Command                 machine LoadPlatformDescription ${PLATFORM}
18    Execute Command                 sysbus.u54_1 ExecutionMode SingleStep
19    Execute Command                 sysbus.u54_2 ExecutionMode SingleStep
20    Execute Command                 sysbus.u54_1 PC 0x80000000
21    Execute Command                 sysbus.u54_2 PC 0x80000100
22
23Assemble Instruction
24    [Arguments]                     ${cpu}  ${mnemonic}  ${operands}=  ${address}=0
25    ${len}=                         Execute Command  sysbus.${cpu} AssembleBlock ${address} "${mnemonic} ${operands}"
26
27Create Reservations
28    # Just write 5 to memory, we'll use this to check for successful and failed writes
29    Execute Command                 sysbus WriteDoubleWord ${VARIABLE_ADDRESS_CPU1} 0x5
30    Execute Command                 sysbus WriteDoubleWord ${VARIABLE_ADDRESS_CPU2} 0x5
31
32    # Make a0 hold the memory address
33
34    # li a0, ${VARIABLE_ADDRESS_CPU1} (two instructions)
35    Assemble Instruction            u54_1  li  a0, ${VARIABLE_ADDRESS_CPU1}  0x80000000
36    Execute Command                 sysbus.u54_1 Step 2
37    Register Should Be Equal        ${a0}  ${VARIABLE_ADDRESS_CPU1}  cpuName=u54_1
38
39    # li a0, ${VARIABLE_ADDRESS_CPU2} (three instructions)
40    Assemble Instruction            u54_2  li  a0, ${VARIABLE_ADDRESS_CPU2}  0x80000100
41    Execute Command                 sysbus.u54_2 Step 3
42    Register Should Be Equal        ${a0}  ${VARIABLE_ADDRESS_CPU2}  cpuName=u54_2
43
44    # Create reservation on first core
45    Assemble Instruction            u54_1  lr.d  a1, (a0)  0x80000006
46    Execute Command                 sysbus.u54_1 Step
47    Register Should Be Equal        ${a1}  0x5  cpuName=u54_1
48
49    # Create reservation on second core
50    Assemble Instruction            u54_2  lr.d  a1, (a0)  0x8000010A
51    Execute Command                 sysbus.u54_2 Step
52    Register Should Be Equal        ${a1}  0x5  cpuName=u54_2
53
54*** Test Cases ***
55Should Handle Multiple Writes To Same Reservation
56    Create Machine
57    Create Reservations
58
59    # Try to update memory address with number 6
60    # This will check if simple LR/SC behaves correctly
61
62    Assemble Instruction            u54_1  li  a2, 0x6  0x8000000A
63    Execute Command                 sysbus.u54_1 Step
64    Register Should Be Equal        ${a2}  0x6  cpuName=u54_1
65
66    # Check for successful SC
67    Assemble Instruction            u54_1  sc.d  a3, a2, (a0)  0x8000000C
68    Execute Command                 sysbus.u54_1 Step
69    Register Should Be Equal        ${a3}  0x0  cpuName=u54_1
70
71    ${res}=                         Execute Command  sysbus ReadDoubleWord ${VARIABLE_ADDRESS_CPU1}
72    Should Be Equal As Integers     ${res}  6
73
74    # Try to SC on something that isn't reserved - this should fail (returns 1)
75
76    Assemble Instruction            u54_1  sc.d  a3, zero, (a0)  0x80000010
77    Execute Command                 sysbus.u54_1 Step
78
79    # Check if SC failed (correct behavior)
80    Register Should Be Equal        ${a3}  0x1  cpuName=u54_1
81
82    ${res}=                         Execute Command  sysbus ReadDoubleWord ${VARIABLE_ADDRESS_CPU1}
83    Should Be Equal As Integers     ${res}  0x00000006
84
85Should Work On Multiple Cores
86    Create Machine
87    Create Reservations
88
89    # Having reservations on two cores, we try to store on both of them
90
91    Assemble Instruction            u54_1  li  a2, 0x6  0x8000000A
92    Execute Command                 sysbus.u54_1 Step
93    Register Should Be Equal        ${a2}  0x6  cpuName=u54_1
94
95    Assemble Instruction            u54_2  li  a2, 0x7  0x8000010E
96    Execute Command                 sysbus.u54_2 Step
97    Register Should Be Equal        ${a2}  0x7  cpuName=u54_2
98
99    # Check for successful store on second core
100    Assemble Instruction            u54_2  sc.d  a3, a2, (a0)  0x80000110
101    Execute Command                 sysbus.u54_2 Step
102    Register Should Be Equal        ${a3}  0x0  cpuName=u54_2
103
104    # Check for successful store on first core
105    Assemble Instruction            u54_1  sc.d  a3, a2, (a0)  0x8000000C
106    Execute Command                 sysbus.u54_1 Step
107    Register Should Be Equal        ${a3}  0x0  cpuName=u54_1
108
109Should Drop Other Core Reservation On SC
110    Create Machine
111    Create Reservations
112
113    # Check if SC on other core's LR will drop the reservation
114
115    Assemble Instruction            u54_1  li  a2, 0x6  0x8000000A
116    Execute Command                 sysbus.u54_1 Step
117    Register Should Be Equal        ${a2}  0x6  cpuName=u54_1
118
119    # Get the address of second core's reservation to first core's a0
120    Assemble Instruction            u54_1  li  a0, ${VARIABLE_ADDRESS_CPU2}  0x8000000C
121    Execute Command                 sysbus.u54_1 Step 3
122    Register Should Be Equal        ${a0}  ${VARIABLE_ADDRESS_CPU2}  cpuName=u54_1
123
124    # Try to store on second core's reservation
125    Assemble Instruction            u54_1  sc.d  a3, a2, (a0)  0x80000016
126    Execute Command                 sysbus.u54_1 Step
127    Register Should Be Equal        ${a3}  0x1  cpuName=u54_1
128
129    # Try to store on second core's reservation by second core
130    Assemble Instruction            u54_2  sc.d  a3, a2, (a0)  0x80000110
131    Execute Command                 sysbus.u54_2 Step
132    Register Should Be Equal        ${a3}  0x0  cpuName=u54_2
133