1*** Keywords ***
2Create RISC-V With ISA String
3    [Arguments]                     ${ISAString}
4    Execute Command                 mach create
5    Execute Command                 logLevel 0
6    Execute Command                 machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"${ISAString}\\"}"
7
8Create RISC-V64 With ISA String
9    [Arguments]                     ${ISAString}
10    Execute Command                 mach create
11    Execute Command                 logLevel 0
12    Execute Command                 machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV64 @ sysbus { cpuType: \\"${ISAString}\\"}"
13
14Should Throw Construction Exception
15    [Arguments]                     ${ISAString}    ${exceptionMsg}
16    Execute Command                 mach create
17    Execute Command                 logLevel 0
18    ${out}=                         Run Keyword And Expect Error  KeywordException:*
19    ...                             Execute Command          machine LoadPlatformDescriptionFromString "cpu: CPU.RiscV32 @ sysbus { cpuType: \\"${ISAString}\\"}"
20    Should Contain                  ${out}      ${exceptionMsg}
21
22*** Test Cases ***
23Should Parse All Valid ISA Strings
24    [Template]                      Create RISC-V With ISA String
25    RV32G
26    rv32gc
27    rv32gc
28    RV32GC
29    rv32gc_xandes
30    RV32GC_Xandes
31    RV32GC_Zicsr_Zifencei
32    RV32G_V
33    rv32ia_zicsr_zifencei
34    RV32IM
35    RV32IMAC
36    RV32IMACB_Zicsr_Zifencei
37    RV32IMACFD_Zicsr
38    RV32IMACFD_Zicsr_Zifencei
39    rv32imac_zicsr
40    RV32_IMACZicsr_Zifencei
41    RV32IMAC_Zicsr_Zifencei
42    RV32IMACZicsr_Zifencei
43    rv32imafc_zifencei
44    rv32imafdcg
45    RV32IMAFDC_Zicsr
46    RV32IMAFDC_Zicsr_Zifencei
47    RV32IMAF_Zicsr_Zifencei
48    rv32ima_zicsr_zifencei
49    RV32IMC
50    rv32imcb_zicsr_zifencei
51    rv32imc_zicsr
52    rv32imc_zicsr_zifencei
53    RV32IMC_Zicsr_Zifencei_Zbs
54    RV32IM_Zicsr
55    rv32im_zicsr_zifencei
56    RV32IZifencei_Xandes
57    rv32ea_zicsr_zifencei
58    RV32EM
59    RV32EMAC
60    rv32emac_zicsr
61    RV32_EMACZicsr_Zifencei
62    RV32EMAC_Zicsr_Zifencei
63    RV32EMACZicsr_Zifencei
64    rv32ema_zicsr_zifencei
65    RV32EMC
66    rv32emc_zicsr
67    rv32emc_zicsr_zifencei
68    RV32EMC_Zicsr_Zifencei_Zbs
69    RV32EM_Zicsr
70    rv32em_zicsr_zifencei
71    RV32EZifencei_Xandes
72
73Should Handle Both 32 And 64 Bit Versions
74    Create RISC-V With ISA String   RV32IMAFDC_Zicsr_Zifencei
75    Create RISC-V64 With ISA String  RV64IMAFDC_Zicsr_Zifencei
76
77Should Throw Construction Exception
78    [Template]                      Should Throw Construction Exception
79    RV32IE    ISA string cannot contain both I and E base instruction sets at the same time
80    RV32EI    ISA string cannot contain both I and E base instruction sets at the same time
81    RV32EF    RV32E can only have M, A and C standard extensions
82    RV32FE    RV32E can only have M, A and C standard extensions
83