1mach create
2include @scripts/single-node/bus-isolation/SampleStateAwareReaderWithTransactionState.cs
3include @scripts/single-node/bus-isolation/SampleStateAwareReader.cs
4include @scripts/single-node/bus-isolation/SampleStateAwarePeripheral.cs
5machine LoadPlatformDescriptionFromString """
6cpu0: CPU.CortexM @ sysbus
7    cpuType: "cortex-m33"
8    numberOfMPURegions: 8
9    nvic: nvic
10    enableTrustZone: true
11
12nvic: IRQControllers.NVIC @ sysbus 0xe000e000
13    -> cpu0@0
14
15flash0: Memory.MappedMemory @ sysbus 0x8000000
16    size: 0x80000
17"""
18using sysbus
19
20# Look at SampleStateAwarePeripheral for an example of implementing different peripheral behavior based on the
21# transaction initiator and/or its state, and SampleStateAwareReader for an example of performing a transaction
22# with specified initiator identity.
23
24# Of course, 2 peripherals can be registered at the same address as long as they require a different cpu
25# state. See the `priv2_` ones as an example.
26machine LoadPlatformDescriptionFromString """
27unpriv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10000; condition: "(cpuSecure || !privileged) && initiator == cpu0" }
28    size: 0x4
29    initable: false
30    script: "request.value = 0x1010"
31
32priv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10004; condition: "cpuSecure && privileged && initiator == cpu0" }
33    size: 0x4
34    initable: false
35    script: "request.value = 0x2020"
36
37both: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10008 }
38    size: 0x4
39    initable: false
40    script: "request.value = 0x3030"
41
42priv2_priv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x1000c; condition: "privileged" }
43    size: 0x4
44    initable: false
45    script: "request.value = 0x4444"
46
47priv2_unpriv: Python.PythonPeripheral @ sysbus new Bus.BusPointRegistration { address: 0x1000c; condition: "!privileged" }
48    size: 0x4
49    initable: false
50    script: "request.value = 0x0404"
51
52priv_aware: CPU.SampleStateAwarePeripheral @ sysbus new Bus.BusPointRegistration { address: 0x10010; condition: "initiator == cpu0 || initiator == reader || initiator == reader2" }
53    size: 0x100
54
55priv_aware2: CPU.SampleStateAwarePeripheral @ sysbus new Bus.BusPointRegistration { address: 0x20010; condition: "cpuSecure && initiator == reader" }
56    size: 0x100
57
58reader: CPU.SampleStateAwareReaderWithTransactionState @ sysbus
59reader2: CPU.SampleStateAwareReader @ sysbus
60reader3: CPU.SampleStateAwareReader @ sysbus
61"""
62
63
64cpu0 AssembleBlock 0x8000000 """
65// First read in privileged mode
66ldr r0, =0x10000
67ldr r3, [r0]       // expect 0x1010 in secure, 0 in nonsecure
68ldr r4, [r0, #4]   // expect 0x2020 in secure, 0 in nonsecure
69ldr r5, [r0, #8]   // expect 0x3030
70ldr r6, [r0, #12]  // expect 0x4444
71ldr r7, [r0, #16]  // expect 0x63707507 in secure, 0x63707501 in nonsecure
72ldr r8, [r0, #20]  // expect 0x63707507 in secure, 0x63707501 in nonsecure
73
74// Switch to unprivileged mode
75mrs r2, CONTROL
76orr r2, r2, #1
77msr CONTROL, r2
78isb
79
80// Reread in unprivileged mode
81ldr r9, [r0]       // expect 0x1010 in both S and NS
82ldr r10, [r0, #4]  // expect 0 in both S and NS
83ldr r11, [r0, #8]  // expect 0x3030
84ldr r12, [r0, #12] // expect 0x0404
85ldr r13, [r0, #16] // expect 0x63707506 in secure, 0x63707500 in nonsecure
86ldr r14, [r0, #20] // expect 0x63707506 in secure, 0x63707500 in nonsecure
87
88b .
89"""
90
91cpu0 IDAUEnabled true
92cpu0 TryAddImplementationDefinedExemptionRegion 0x8000000 0x80000ff
93cpu0 TryAddImplementationDefinedExemptionRegion 0x10000 0x100ff
94cpu0 PC 0x8000000
95