1*** Variables *** 2${URI} @https://dl.antmicro.com/projects/renode 3${PROMPT} zynq> 4${UART} sysbus.uart0 5${SCRIPT} ${CURDIR}/../../../scripts/single-node/zynq_verilated_fpga_isp.resc 6${PLATFORM} @platforms/boards/mars_zx3.repl 7${FPGA_ISP_NATIVE_LINUX} ${URI}/libVfpga_isp-Linux-x86_64-12904733885.so-s_2507680-9d567ef5ddf2569d75b2d90abd6acbfe12ffbfd4 8${FPGA_ISP_NATIVE_WINDOWS} ${URI}/libVfpga_isp-Windows-x86_64-12904733885.dll-s_3690794-0986cf74a6351ec50710e40372316d5712659531 9${FPGA_ISP_NATIVE_MACOS} ${URI}/libVfpga_isp-macOS-x86_64-12904733885.dylib-s_470408-8a990124cc9ce7bd7235bef19210c2b99ba31131 10${BIN_VM} ${URI}/zynq-verilated-fpga-isp--vmlinux-s_13735336-6a3e10bd5b6d301cc8846490cad6de9ec541e067 11${ROOTFS} ${URI}/zynq-verilated-fpga-isp--rootfs.ext2-s_33554432-cc9664564461b5be36a4d1841e50a760dc7f5ad1 12${DTB} ${URI}/zynq-verilated-fpga-isp--video-board.dtb-s_13451-bdb696327471e2247f811b03f37be84df994379a 13${VIRTIO} ${URI}/empty-ext4-filesystem.img-s_33554432-1eb65a808612389cc35a69b81178fbad5708a863 14${FASTVDMA_DRIVER} /lib/modules/5.15.0-xilinx/kernel/drivers/dma/fastvdma/fastvdma.ko 15${DEMOSAICER_DRIVER} /lib/modules/5.15.0-xilinx/kernel/drivers/media/platform/demosaicer/zynq_demosaicer.ko 16 17*** Keywords *** 18Create Machine 19 Execute Command \$ispLinux?=${FPGA_ISP_NATIVE_LINUX} 20 Execute Command \$ispWindows?=${FPGA_ISP_NATIVE_WINDOWS} 21 Execute Command \$ispMacOS?=${FPGA_ISP_NATIVE_MACOS} 22 Execute Script ${SCRIPT} 23 Create Terminal Tester ${UART} 24 25Should Load Drivers 26 [Documentation] Loads fastvdma.ko and zynq_demosaicer.ko drivers. 27 28 # Suppress messages from kernel space so it doesn't affect dd and cmp outputs 29 Write Line To Uart echo 0 > /proc/sys/kernel/printk 30 31 # It seems like the simulated shell splits long lines what messes with `waitForEcho` in the terminal tester 32 Write Line To Uart insmod ${FASTVDMA_DRIVER} waitForEcho=false 33 Wait For Prompt On Uart ${PROMPT} 34 35 Write Line To Uart insmod ${DEMOSAICER_DRIVER} waitForEcho=false 36 Wait For Prompt On Uart ${PROMPT} 37 38 Write Line To Uart lsmod 39 Wait For Line On Uart Module 40 Wait For Line On Uart zynq_demosaicer 41 Wait For Line On Uart fastvdma 42 43Should Run v4l2-ctl and Debayer Images 44 [Documentation] Sets image to FPGA ISP input, runs v4l2-ctl and transfers said image through FPGA ISP which debayers it and saves the output. 45 46 Write Line To Uart ./write_image 47 Wait For Prompt On Uart ${PROMPT} 48 49 Write Line To Uart v4l2-ctl -d0 --set-fmt-video=width=600,height=398,pixelformat=RGB4 --stream-mmap --stream-count=1 --stream-to=out0.rgb waitForEcho=false 50 Wait For Line On Uart < timeout=300 51 Wait For Prompt On Uart ${PROMPT} timeout=100 52 53 Write Line To Uart v4l2-ctl -d0 --set-fmt-video=width=600,height=398,pixelformat=RGB4 --stream-mmap --stream-count=1 --stream-to=out1.rgb waitForEcho=false 54 Wait For Line On Uart < timeout=300 55 Wait For Prompt On Uart ${PROMPT} timeout=100 56 57Verify Images 58 [Documentation] Verifies whether the image has been transferred correctly. 59 60 # Verify if the images were debayered correctly 61 Write Line To Uart cmp -s out0.rgb out1.rgb && echo "CMP success" || echo "CMP failure" waitForEcho=false 62 Wait For Line On Uart CMP success 63 64*** Test Cases *** 65 66FPGA ISP Debayer On Native Communication 67 [Documentation] Test FPGA ISP debayering. 68 [Tags] skip_host_arm 69 70 Create Machine 71 Start Emulation 72 Wait For Prompt On Uart ${PROMPT} timeout=300 73 Should Load Drivers 74 Should Run v4l2-ctl and Debayer Images 75 Verify Images 76