1********************************** Variables ********************************** 2 3${UART} sysbus.uart0 4${URI} @https://dl.antmicro.com/projects/renode 5 6### CPSR 7 8${CPSR_N_MASK} ${{ 0x1 << 31 }} 9${CPSR_Z_MASK} ${{ 0x1 << 30 }} 10${CPSR_C_MASK} ${{ 0x1 << 29 }} 11${CPSR_V_MASK} ${{ 0x1 << 28 }} 12${CPSR_Q_MASK} ${{ 0x1 << 27 }} 13${CPSR_SSBS_MASK} ${{ 0x1 << 23 }} 14${CPSR_PAN_MASK} ${{ 0x1 << 22 }} 15${CPSR_IL_MASK} ${{ 0x1 << 20 }} 16${CPSR_GE_MASK} ${{ 0xF << 16 }} 17${CPSR_E_MASK} ${{ 0x1 << 9 }} 18${CPSR_A_MASK} ${{ 0x1 << 8 }} 19${CPSR_I_MASK} ${{ 0x1 << 7 }} 20${CPSR_F_MASK} ${{ 0x1 << 6 }} 21${CPSR_T_MASK} ${{ 0x1 << 5 }} 22${CPSR_MODE_MASK} ${{ 0x1F << 0 }} 23 24${INITIAL_CPSR_T_VALUE} 0x0 25${INITIAL_CPSR_E_VALUE} 0x0 26 27### SCTLR 28 29${SCTLR_V_MASK} ${{ 1 << 13 }} 30${SCTLR_M_MASK} ${{ 1 << 0 }} 31 32### Privilege Level 33 34@{AVAILABLE_PRIVILEGE_LEVELS} User 35... FIQ 36... IRQ 37... Supervisor 38... Abort 39... Hypervisor 40... Undefined 41... System 42 43@{UNAVAILABLE_PRIVILEGE_LEVELS} Monitor 44${HIGHEST_PRIVILEGE_LEVEL} Hypervisor 45 46### Exceptions 47 48@{AVAILABLE_ASYNCHRONOUS_EXCEPTIONS} IRQ FIQ 49@{AVAILABLE_SYNCHRONOUS_EXCEPTIONS} UNDEFINED_INSTRUCTION 50 51### Hivecs 52 53${HIVECS_BASE_ADDRESS} 0xFFFF0000 54${HIVECS_DUMMY_MEMORY} SEPARATOR= 55... """ ${\n} 56... dummy_memory: Memory.MappedMemory @ sysbus ${HIVECS_BASE_ADDRESS} ${\n} 57... \ \ \ \ size: 0x1000 ${\n} 58... """ 59 60 61### SMP 62 63${GIC_V2_SMP} SEPARATOR= 64... """ ${\n} 65... using "platforms/cpus/cortex-r52_smp_4.repl" ${\n} 66... ${\n} 67... gic: @ { ${\n} 68... ${SPACE*4}sysbus new Bus.BusMultiRegistration { address: 0xAF000000; size: 0x010000; region: \"distributor\" }; ${\n} 69... ${SPACE*4}sysbus new Bus.BusMultiRegistration { address: 0xAF100000; size: 0x200000; region: \"cpuInterface\" } ${\n} 70... } ${\n} 71... ${SPACE*4}architectureVersion: IRQControllers.ARM_GenericInterruptControllerVersion.GICv2 ${\n} 72... """ 73 74*********************************** Keywords ********************************** 75 76### Stateless Keywords (do not depend on the current state of the simulation) 77 78Get Updated Register Value 79 [Arguments] ${reg_val} ${mask} ${new_val} 80 ${result}= Set Variable ${{ (${reg_val} & ~${mask}) | (${new_val} & ${mask}) }} 81 RETURN ${result} 82 83Get Register Field Value 84 [Arguments] ${reg_val} ${mask} 85 ${result}= Set Variable ${{ ${reg_val} & ${mask} }} 86 RETURN ${result} 87 88Get CPSR Field Value 89 [Arguments] ${cpsr} ${field} 90 IF "${field}" == "N" 91 ${result}= Get Register Field Value ${cpsr} ${CPSR_N_MASK} 92 ELSE IF "${field}" == "Z" 93 ${result}= Get Register Field Value ${cpsr} ${CPSR_Z_MASK} 94 ELSE IF "${field}" == "C" 95 ${result}= Get Register Field Value ${cpsr} ${CPSR_C_MASK} 96 ELSE IF "${field}" == "V" 97 ${result}= Get Register Field Value ${cpsr} ${CPSR_V_MASK} 98 ELSE IF "${field}" == "Q" 99 ${result}= Get Register Field Value ${cpsr} ${CPSR_Q_MASK} 100 ELSE IF "${field}" == "SSBS" 101 ${result}= Get Register Field Value ${cpsr} ${CPSR_SSBS_MASK} 102 ELSE IF "${field}" == "PAN" 103 ${result}= Get Register Field Value ${cpsr} ${CPSR_PAN_MASK} 104 ELSE IF "${field}" == "IL" 105 ${result}= Get Register Field Value ${cpsr} ${CPSR_IL_MASK} 106 ELSE IF "${field}" == "GE" 107 ${result}= Get Register Field Value ${cpsr} ${CPSR_GE_MASK} 108 ELSE IF "${field}" == "E" 109 ${result}= Get Register Field Value ${cpsr} ${CPSR_E_MASK} 110 ELSE IF "${field}" == "A" 111 ${result}= Get Register Field Value ${cpsr} ${CPSR_A_MASK} 112 ELSE IF "${field}" == "I" 113 ${result}= Get Register Field Value ${cpsr} ${CPSR_I_MASK} 114 ELSE IF "${field}" == "F" 115 ${result}= Get Register Field Value ${cpsr} ${CPSR_F_MASK} 116 ELSE IF "${field}" == "T" 117 ${result}= Get Register Field Value ${cpsr} ${CPSR_T_MASK} 118 ELSE IF "${field}" == "M" or "${field}" == "MODE" 119 ${result}= Get Register Field Value ${cpsr} ${CPSR_MODE_MASK} 120 ELSE 121 Fail Unexpected CPSR Field Name: "${field}" 122 END 123 RETURN ${result} 124 125Get CPSR Mode Value From Privilege Level Name 126 [Arguments] ${pl} 127 IF "${pl}" == "User" or "${pl}" == "USR" 128 ${result}= Convert To Integer 0b10000 129 ELSE IF "${pl}" == "FIQ" 130 ${result}= Convert To Integer 0b10001 131 ELSE IF "${pl}" == "IRQ" 132 ${result}= Convert To Integer 0b10010 133 ELSE IF "${pl}" == "Supervisor" or "${pl}" == "SVC" 134 ${result}= Convert To Integer 0b10011 135 ELSE IF "${pl}" == "Monitor" or "${pl}" == "MON" 136 ${result}= Convert To Integer 0b10110 137 ELSE IF "${pl}" == "Abort" or "${pl}" == "ABT" 138 ${result}= Convert To Integer 0b10111 139 ELSE IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 140 ${result}= Convert To Integer 0b11010 141 ELSE IF "${pl}" == "Undefined" or "${pl}" == "UND" 142 ${result}= Convert To Integer 0b11011 143 ELSE IF "${pl}" == "System" or "${pl}" == "SYS" 144 ${result}= Convert To Integer 0b11111 145 ELSE 146 Fail Unexpected Privilege Level Name: "${pl}" 147 END 148 RETURN ${result} 149 150Get CPSR For Changed Privilege Level 151 [Arguments] ${pl} ${cpsr} 152 ${mode_val}= Get CPSR Mode Value From Privilege Level Name ${pl} 153 ${new_cpsr}= Get Updated Register Value ${cpsr} ${CPSR_MODE_MASK} ${mode_val} 154 RETURN ${new_cpsr} 155 156Get CPSR After Changing To Wrong Mode 157 [Arguments] ${old_cpsr} ${new_cpsr} 158 ${mask}= Set Variable ${{ ~${CPSR_MODE_MASK} }} 159 ${new_cpsr} Set Variable ${{ ${new_cpsr} | ${CPSR_IL_MASK} }} 160 ${result}= Get Updated Register Value ${old_cpsr} ${mask} ${new_cpsr} 161 RETURN ${result} 162 163Get Exception Handler Offset From Hypervisor Vector Table 164 [Arguments] ${exception_type} 165 IF "${exception_type}" == "UNDEFINED_INSTRUCTION" 166 ${offset}= Convert To Integer 0x4 167 ELSE IF "${exception_type}" == "HYPERVISOR_CALL" 168 ${offset}= Convert To Integer 0x8 169 ELSE IF "${exception_type}" == "PREFETCH_ABORT" 170 ${offset}= Convert To Integer 0xc 171 ELSE IF "${exception_type}" == "DATA_ABORT" 172 ${offset}= Convert To Integer 0x10 173 ELSE IF "${exception_type}" == "HYP_TRAP" 174 ${offset}= Convert To Integer 0x14 175 ELSE IF "${exception_type}" == "IRQ" 176 ${offset}= Convert To Integer 0x18 177 ELSE IF "${exception_type}" == "FIQ" 178 ${offset}= Convert To Integer 0x1c 179 ELSE 180 Fail Unexpected Exception Type Name: "${exception_type}" 181 END 182 RETURN ${offset} 183 184Get Exception Handler Offset From Non-Secure Vector Table 185 [Arguments] ${exception_type} 186 IF "${exception_type}" == "UNDEFINED_INSTRUCTION" 187 ${offset}= Convert To Integer 0x4 188 ELSE IF "${exception_type}" == "SUPERVISOR_CALL" 189 ${offset}= Convert To Integer 0x8 190 ELSE IF "${exception_type}" == "PREFETCH_ABORT" 191 ${offset}= Convert To Integer 0xc 192 ELSE IF "${exception_type}" == "DATA_ABORT" 193 ${offset}= Convert To Integer 0x10 194 ELSE IF "${exception_type}" == "IRQ" 195 ${offset}= Convert To Integer 0x18 196 ELSE IF "${exception_type}" == "FIQ" 197 ${offset}= Convert To Integer 0x1c 198 ELSE 199 Fail Unexpected Exception Type Name: "${exception_type}" 200 END 201 RETURN ${offset} 202 203Get Exception Handler Offset 204 [Arguments] ${pl} ${excp_type} 205 IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 206 ${offset}= Get Exception Handler Offset From Hypervisor Vector Table ${excp_type} 207 ELSE 208 ${offset}= Get Exception Handler Offset From Non-Secure Vector Table ${excp_type} 209 END 210 RETURN ${offset} 211 212Convert Integer To Hex String 213 [Arguments] ${value} 214 ${result}= Convert To Hex ${value} prefix=0x 215 RETURN ${result} 216 217Contains Substring 218 [Arguments] ${str} ${substr} 219 ${result}= Run Keyword And Return Status Should Contain ${str} ${substr} 220 RETURN ${result} 221 222### Stateful Keywords (they depend on the current state of the simulation) 223 224Get Current CPSR Value 225 ${cpsr}= Execute Command sysbus.cpu CPSR 226 ${cpsr}= Convert To Integer ${cpsr} 227 RETURN ${cpsr} 228 229Set Current CPSR Value 230 [Arguments] ${value} 231 ${value_str}= Convert Integer To Hex String ${value} 232 Execute Command sysbus.cpu CPSR ${value_str} 233 234Get Current Privilege Level Value 235 ${cpsr}= Get Current CPSR Value 236 ${mode}= Get Register Field Value ${cpsr} ${CPSR_MODE_MASK} 237 RETURN ${mode} 238 239Set Current Privilege Level Value 240 [Arguments] ${pl} 241 ${current_cpsr}= Get Current CPSR Value 242 ${new_cpsr}= Get CPSR For Changed Privilege Level ${pl} ${current_cpsr} 243 ${new_cpsr}= Convert Integer To Hex String ${new_cpsr} 244 Execute Command sysbus.cpu CPSR ${new_cpsr} 245 246Get Current PC Value 247 ${pc}= Execute Command sysbus.cpu PC 248 ${pc}= Convert To Integer ${pc} 249 RETURN ${pc} 250 251Set Current PC Value 252 [Arguments] ${value} 253 ${value_str}= Convert Integer To Hex String ${value} 254 Execute Command sysbus.cpu PC ${value_str} 255 256Get Current CPSR Field Value 257 [Arguments] ${field} 258 ${cpsr}= Get Current CPSR Value 259 ${result}= Get CPSR Field Value ${cpsr} ${field} 260 RETURN ${result} 261 262Get Current System Register Value 263 [Arguments] ${reg_name} 264 ${reg_value}= Execute Command sysbus.cpu GetSystemRegisterValue \"${reg_name}\" 265 ${result}= Convert To Integer ${reg_value} 266 Check For Register Errors In Last Log ${reg_name} 267 RETURN ${result} 268 269Set Current System Register Value 270 [Arguments] ${reg_name} ${value} 271 ${value_str}= Convert Integer To Hex String ${value} 272 Execute Command sysbus.cpu SetSystemRegisterValue \"${reg_name}\" ${value_str} 273 Check For Register Errors In Last Log ${reg_name} 274 275Set Asynchronous Exception 276 [Arguments] ${exception_type} 277 IF "${exception_type}" == "IRQ" 278 Execute Command sysbus.cpu OnGPIO 0 True 279 ELSE IF "${exception_type}" == "FIQ" 280 Execute Command sysbus.cpu OnGPIO 1 True 281 ELSE 282 Fail Unexpected Exception Type Name: "${exception_type}" 283 END 284 285Set Synchronous Exception 286 [Arguments] ${exception_type} 287 IF "${exception_type}" == "UNDEFINED_INSTRUCTION" 288 ${pc}= Get Current PC Value 289 Write Opcode To Address ${pc} 0xDEADBEEF 290 Execute Command sysbus.cpu Step 291 ELSE IF "${exception_type}" == "HYPERVISOR_CALL" 292 Fail Forcing "${exception_type}" is not supported 293 ELSE IF "${exception_type}" == "SUPERVISOR_CALL" 294 Fail Forcing "${exception_type}" is not supported 295 ELSE IF "${exception_type}" == "PREFETCH_ABORT" 296 Fail Forcing "${exception_type}" is not supported 297 ELSE IF "${exception_type}" == "DATA_ABORT" 298 Fail Forcing "${exception_type}" is not supported 299 ELSE 300 Fail Unexpected Exception Type Name: "${exception_type}" 301 END 302 303Set Exception Vector Base Address 304 [Arguments] ${pl} ${base_address} 305 IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 306 Set Current System Register Value HVBAR ${base_address} # exceptions taken to hypervisor mode 307 ELSE 308 Set Current System Register Value VBAR ${base_address} # exceptions taken to non-secure mode 309 END 310 311Reset CPU 312 Execute Command sysbus.cpu Reset 313 314Enable Hivecs 315 ${sctlr}= Get Current System Register Value SCTLR 316 ${sctlr}= Get Updated Register Value ${sctlr} ${SCTLR_V_MASK} ${SCTLR_V_MASK} 317 Set Current System Register Value SCTLR ${sctlr} 318 319Enable EL2 MPU 320 ${sctlr}= Get Current System Register Value HSCTLR 321 ${sctlr}= Get Updated Register Value ${sctlr} ${SCTLR_M_MASK} ${SCTLR_M_MASK} 322 Set Current System Register Value HSCTLR ${sctlr} 323 324Enable EL1 MPU 325 ${sctlr}= Get Current System Register Value SCTLR 326 ${sctlr}= Get Updated Register Value ${sctlr} ${SCTLR_M_MASK} ${SCTLR_M_MASK} 327 Set Current System Register Value SCTLR ${sctlr} 328 329Unmask Exception 330 [Arguments] ${excp_name} 331 ${mask} Set Variable 0x0 332 IF "${excp_name}" == "A" or "${excp_name}" == "SERROR" 333 ${mask}= Set Variable ${{ ${mask} | ${CPSR_A_MASK} }} 334 END 335 IF "${excp_name}" == "I" or "${excp_name}" == "IRQ" 336 ${mask}= Set Variable ${{ ${mask} | ${CPSR_I_MASK} }} 337 END 338 IF "${excp_name}" == "F" or "${excp_name}" == "FIQ" 339 ${mask}= Set Variable ${{ ${mask} | ${CPSR_F_MASK} }} 340 END 341 ${cpsr}= Get Current CPSR Value 342 ${new_cpsr}= Get Updated Register Value ${cpsr} ${mask} 0 343 Set Current CPSR Value ${new_cpsr} 344 345Check For Register Errors In Last Log 346 [Arguments] ${reg_name} 347 ${log}= Execute Command lastLog 1 348 ${contains_reg_error} Contains Substring ${log} system register failure 349 ${contains_reg_name} Contains Substring ${log} ${reg_name} 350 IF ${contains_reg_error} and ${contains_reg_name} 351 Fail "${reg_name}" register does not exist! 352 END 353 354Write Opcode To Address 355 [Arguments] ${address} ${opcode} 356 Execute Command sysbus WriteDoubleWord ${address} ${opcode} 357 358Current Privilege Level Should Be 359 [Arguments] ${pl} 360 ${current_pl}= Get Current Privilege Level Value 361 ${expected_pl}= Get CPSR Mode Value From Privilege Level Name ${pl} 362 Should Be Equal As Integers ${current_pl} ${expected_pl} 363 364Current PC Should Be 365 [Arguments] ${expected_pc} 366 ${current_pc}= Get Current PC Value 367 Should Be Equal As Integers ${current_pc} ${expected_pc} 368 369Current CPSR Should Be 370 [Arguments] ${expected_cpsr} 371 ${cpsr}= Get Current CPSR Value 372 Should Be Equal As Integers ${cpsr} ${expected_cpsr} 373 374Current CPSR Field Should Be 375 [Arguments] ${field} ${expected_value} 376 ${val}= Get Current CPSR Field Value ${field} 377 Should Be Equal As Integers ${val} ${expected_value} 378 379Current CPSR Flag Should Be Set 380 [Arguments] ${flag} 381 ${val}= Get Current CPSR Field Value ${flag} 382 Should Be Equal As Integers ${val} 1 383 384Current CPSR Flag Should Be Unset 385 [Arguments] ${flag} 386 ${val}= Get Current CPSR Field Value ${flag} 387 Should Be Equal As Integers ${val} 0 388 389Current System Register Value Should Be 390 [Arguments] ${reg_name} ${expected_value} 391 ${reg_value}= Get Current System Register Value ${reg_name} 392 Should Be Equal As Integers ${reg_value} ${expected_value} 393 394### Auxiliary Keywords (not general keywords used to simplify test cases) 395 396Initialize Emulation 397 [Arguments] ${exec_mode}=Continuous ${pl}=default ${pc}=default ${elf}=default 398 ... ${binary}=default ${create_uart_tester}=False ${map_memory}=False 399 400 # Tests assume Renode prints HEX numbers. 401 Execute Command numbersMode Hexadecimal 402 403 Execute Command mach create 404 Execute Command machine LoadPlatformDescription @platforms/cpus/cortex-r52.repl 405 Execute Command sysbus.cpu ExecutionMode ${exec_mode} 406 407 # Map all addresses as read/write and executable for EL2, EL1, and EL0 408 IF ${map_memory} 409 # Set Attr0 to Normal, Outer-Read and -Write 410 Set Current System Register Value MAIR0 0x70 411 # Set base address to 0, Outer Shareable, and Read-Write at EL1 and EL0, and disable execute never 412 Set Current System Register Value PRBAR 0x12 413 # Set limit address to 0xFFFFFFFF, select Attr0, and enable the region 414 Set Current System Register Value PRLAR 0xFFFFFFC1 415 Enable EL1 MPU 416 417 # Set Attr0 to Normal, Outer-Read and -Write 418 Set Current System Register Value HMAIR0 0x70 419 # Set base address to 0, Outer Shareable, and Read-Write at EL2, EL1, and EL0, and disable execute never 420 Set Current System Register Value HPRBAR 0x12 421 # Set limit address to 0xFFFFFFFF, select Attr0, and enable the region 422 Set Current System Register Value HPRLAR 0xFFFFFFC1 423 Enable EL2 MPU 424 END 425 426 IF "${elf}" != "default" 427 Execute Command sysbus LoadELF ${elf} 428 END 429 IF "${binary}" != "default" 430 Execute Command sysbus LoadBinary ${binary} 431 END 432 433 IF "${pl}" != "default" 434 Set Current Privilege Level Value ${pl} 435 Current Privilege Level Should Be ${pl} 436 END 437 IF "${pc}" != "default" 438 Set Current PC Value ${pc} 439 Current PC Should Be ${pc} 440 END 441 442 IF ${create_uart_tester} 443 Create Terminal Tester ${UART} defaultPauseEmulation=True 444 Execute Command showAnalyzer ${UART} 445 END 446 447Check If CPSR Contains Reset Values 448 Current CPSR Field Should Be A ${CPSR_A_MASK} 449 Current CPSR Field Should Be I ${CPSR_I_MASK} 450 Current CPSR Field Should Be F ${CPSR_F_MASK} 451 Current CPSR Field Should Be IL 0x0 452 Current CPSR Field Should Be T ${INITIAL_CPSR_T_VALUE} 453 Current CPSR Field Should Be E ${INITIAL_CPSR_E_VALUE} 454 455Check If Current PC Equal To RVBAR 456 ${rvbar_value}= Get Current System Register Value RVBAR 457 Current PC Should Be ${rvbar_value} 458 459Add Dummy Memory At Hivecs Base Address 460 Execute Command machine LoadPlatformDescriptionFromString ${HIVECS_DUMMY_MEMORY} 461 462Check Protection Region Address Register Access Through Selector Register 463 [Arguments] ${direct_addr_reg} ${selected_addr_reg} ${selector_reg} ${region_num} ${reserved_mask} 464 ${WRITE_VALUE} Set Variable 0xFFFFFFFF 465 ${EXPECTED_REG_VALUE}= Evaluate 0xFFFFFFFF ^ ${reserved_mask} 466 Set Current System Register Value ${selector_reg} ${region_num} 467 Set Current System Register Value ${selected_addr_reg} ${WRITE_VALUE} 468 ${reg_value}= Get Current System Register Value ${direct_addr_reg} 469 Should Be Equal As Integers ${reg_value} ${EXPECTED_REG_VALUE} 470 471Check Protection Region Address Register Access Through Direct Register 472 [Arguments] ${direct_addr_reg} ${selected_addr_reg} ${region_selector_reg} ${region_num} ${reserved_mask} 473 ${WRITE_VALUE} Set Variable 0xFFFFFFFF 474 ${EXPECTED_REG_VALUE}= Evaluate 0xFFFFFFFF ^ ${reserved_mask} 475 Set Current System Register Value ${direct_addr_reg} ${WRITE_VALUE} 476 Set Current System Register Value ${region_selector_reg} ${region_num} 477 ${reg_value}= Get Current System Register Value ${selected_addr_reg} 478 Should Be Equal As Integers ${reg_value} ${EXPECTED_REG_VALUE} 479 480Check Debug Exceptions Template 481 [Arguments] ${instruction} ${handler_offset} ${DBGDSCRext} ${step} ${return_address} 482 ${HANDLER_ADDRESS}= Set Variable 0x8010 483 484 IF "${instruction}" == "BKPT" 485 ${opcode}= Set Variable 0xE1200070 486 ELSE IF "${instruction}" == "SVC" 487 ${opcode}= Set Variable 0xEF000000 488 ELSE IF "${instruction}" == "HVC" 489 ${opcode}= Set Variable 0xE1400070 490 ELSE 491 Fail Unexpected instruction: "${instruction}" 492 END 493 494 Initialize Emulation pc=0x8000 exec_mode=SingleStep 495 Write Opcode To Address 0x8000 0xE3080010 # mov r0, #0x8010 @ HANDLER_ADDRESS 496 Write Opcode To Address 0x8004 0xEE8C0F10 # mcr p15, 4, r0, c12, c0, 0 @ set HVBAR 497 Write Opcode To Address 0x8008 ${opcode} # instruction #0 498 Write Opcode To Address 0x800C 0xEAFFFFFD # b 0x8008 499 Write Opcode To Address 0x8010 0xE1A00000 # nop 500 Write Opcode To Address 0x8014 0xE1A00000 # nop 501 Write Opcode To Address 0x8018 0xE1A00000 # nop 502 Write Opcode To Address 0x801C 0xE160006E # eret 503 Start Emulation 504 505 Execute Command sysbus.cpu Step 3 506 Current PC Should Be ${{ ${HANDLER_ADDRESS} + ${handler_offset} }} 507 Current System Register Value Should Be DBGDSCRext ${DBGDSCRext} 508 Current CPSR Field Should Be A ${CPSR_A_MASK} 509 Current CPSR Field Should Be I ${CPSR_I_MASK} 510 Current CPSR Field Should Be F ${CPSR_F_MASK} 511 Execute Command sysbus.cpu Step ${step} 512 Current PC Should Be ${return_address} 513 514 [Teardown] Reset Emulation 515 516Check Synchronous Exceptions Handling Template 517 [Arguments] ${pl} ${exception_type} 518 ${EXCEPTION_HANDLER_BASE_ADDRESS}= Set Variable 0x8000 519 ${EXCEPTION_HANDLER_OFFSET}= Get Exception Handler Offset ${pl} ${exception_type} 520 ${EXPECTED_PC}= Set Variable ${{ ${EXCEPTION_HANDLER_BASE_ADDRESS} + ${EXCEPTION_HANDLER_OFFSET} }} 521 522 Initialize Emulation pl=${pl} exec_mode=SingleStep map_memory=True 523 Unmask Exception ${exception_type} 524 Start Emulation 525 526 Set Exception Vector Base Address ${pl} ${EXCEPTION_HANDLER_BASE_ADDRESS} 527 Set Synchronous Exception ${exception_type} 528 Current PC Should Be ${EXPECTED_PC} 529 530 [Teardown] Reset Emulation 531 532Check Asynchronous Exceptions Handling Template 533 [Arguments] ${pl} ${exception_type} 534 ${EXCEPTION_HANDLER_BASE_ADDRESS}= Set Variable 0x8000 535 ${EXCEPTION_HANDLER_OFFSET}= Get Exception Handler Offset ${pl} ${exception_type} 536 ${EXPECTED_PC}= Set Variable ${{ ${EXCEPTION_HANDLER_BASE_ADDRESS} + ${EXCEPTION_HANDLER_OFFSET} }} 537 538 Initialize Emulation pl=${pl} exec_mode=SingleStep 539 Unmask Exception ${exception_type} 540 Start Emulation 541 542 Set Exception Vector Base Address ${pl} ${EXCEPTION_HANDLER_BASE_ADDRESS} 543 Set Asynchronous Exception ${exception_type} 544 Execute Command sysbus.cpu Step 545 546 # FIXME: An artificial 0x4 offset was added because Renode executes 547 # two instructions after entering exception handler with Step command 548 Current PC Should Be ${{ ${EXPECTED_PC} + 0x4 }} 549 550 [Teardown] Reset Emulation 551 552### Template Keywords (keywords used in test templates) 553 554Check Changing Privilege Level From Monitor Template 555 [Arguments] ${pl} 556 557 Initialize Emulation pl=${pl} 558 559Check Value Of System Registers After Initialization Template 560 [Arguments] ${reg_name} ${value} 561 562 Initialize Emulation 563 Current System Register Value Should Be ${reg_name} ${value} 564 565 [Teardown] Reset Emulation 566 567Check Value Of System Registers After Reset Template 568 [Arguments] ${reg_name} ${value} ${access} 569 570 Initialize Emulation 571 IF "${access}" == "RW" 572 Set Current System Register Value ${reg_name} 0xDEADBEEF 573 END 574 575 Reset CPU 576 Current System Register Value Should Be ${reg_name} ${value} 577 578 [Teardown] Reset Emulation 579 580Check Access To SPSR_hyp Register Template 581 [Arguments] ${pl} 582 583 Initialize Emulation pl=${pl} pc=0x8000 exec_mode=SingleStep map_memory=True 584 Write Opcode To Address 0x8000 0xe16ef300 # msr SPSR_hyp, r0 585 Start Emulation 586 587 Execute Command sysbus.cpu Step 588 IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 589 # SPSR_hyp accesses from Hypervisor mode are UNPREDICTABLE. However, a common Cortex-R52 initialization procedure, 590 # that works correctly on hardware and in FVP, sets it so Renode also allows for such accesses. 591 Current Privilege Level Should Be Hypervisor 592 Current PC Should Be 0x8004 593 ELSE 594 # SPSR_hyp access from other Privilege Levels causes 595 # Undefined Instruction Exception handled at Undefined Privilege Level 596 Current Privilege Level Should Be Undefined 597 Current PC Should Be 0x4 598 END 599 600 [Teardown] Reset Emulation 601 602Check Access To ELR_hyp Template 603 [Arguments] ${pl} ${expected_access_allowed} 604 605 Initialize Emulation pl=${pl} pc=0x8000 exec_mode=SingleStep map_memory=True 606 Write Opcode To Address 0x8000 0xe30c0afe # movw r0, #51966 ; 0xcafe 607 Write Opcode To Address 0x8004 0xe12ef300 # msr ELR_hyp, r0 608 Write Opcode To Address 0x8008 0xe10e1300 # mrs r1, ELR_hyp 609 Write Opcode To Address 0x800C 0xe1500001 # cmp r0, r1 610 Start Emulation 611 612 IF ${expected_access_allowed} == True 613 Execute Command sysbus.cpu Step 3 614 Current CPSR Flag Should Be Unset C 615 Current Privilege Level Should Be ${pl} 616 ELSE 617 Execute Command sysbus.cpu Step 2 618 Current PC Should Be 0x4 619 Current Privilege Level Should Be Undefined 620 END 621 622 [Teardown] Reset Emulation 623 624Check CPSR_c Instruction Changing Privilege Level To User Template 625 [Arguments] ${pl} ${expected_access_allowed} 626 ${TARGET_CPSR}= Set Variable 0x40000110 627 ${EXPECTED_PC}= Set Variable 0x8004 628 629 Initialize Emulation pl=${pl} pc=0x8000 exec_mode=SingleStep map_memory=True 630 Write Opcode To Address 0x8000 0xe321f010 # msr CPSR_c, #16 631 Start Emulation 632 633 ${unmodified_cpsr}= Get Current CPSR Value 634 Execute Command sysbus.cpu Step 635 IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 636 ${expected_cpsr}= Get CPSR After Changing To Wrong Mode ${unmodified_cpsr} ${TARGET_CPSR} 637 ELSE 638 IF ${expected_access_allowed} == True 639 ${expected_cpsr}= Set Variable ${TARGET_CPSR} 640 ELSE 641 ${expected_cpsr}= Set Variable ${unmodified_cpsr} 642 END 643 END 644 Current PC Should Be ${EXPECTED_PC} 645 Current CPSR Should Be ${expected_cpsr} 646 647 [Teardown] Reset Emulation 648 649Check VBAR Register Usage By IRQ Template 650 [Arguments] ${pl} 651 ${EXCEPTION_VECTOR_ADDRESS}= Set Variable 0x8000 652 ${IRQ_HANDLER_OFFSET}= Set Variable 0x18 653 ${EXPECTED_PC}= Set Variable ${{ ${EXCEPTION_VECTOR_ADDRESS} + ${IRQ_HANDLER_OFFSET} }} 654 655 Initialize Emulation pl=${pl} exec_mode=SingleStep 656 Unmask Exception IRQ 657 Start Emulation 658 659 Set Exception Vector Base Address ${pl} ${EXCEPTION_VECTOR_ADDRESS} 660 Set Asynchronous Exception IRQ 661 Execute Command sysbus.cpu Step 662 663 # FIXME: An artificial 0x4 offset was added because Renode executes two instructions after entering IRQ handler with Step command 664 Current PC Should Be ${{ ${expected_pc} + 0x4 }} 665 666 [Teardown] Reset Emulation 667 668Check High Exception Vectors Usage By IRQ Template 669 [Arguments] ${pl} 670 ${IRQ_HANDLER_BASE}= Set Variable 0xFFFF0000 671 ${IRQ_HANDLER_OFFSET}= Set Variable 0x18 672 ${EXPECTED_PC}= Set Variable ${{ ${IRQ_HANDLER_BASE} + ${IRQ_HANDLER_OFFSET} }} 673 674 Initialize Emulation pl=${pl} exec_mode=SingleStep map_memory=True 675 Add Dummy Memory At Hivecs Base Address # Prevent CPU abort error when trying to execute code from hivecs addresses 676 Unmask Exception IRQ 677 Enable Hivecs 678 Start Emulation 679 680 Set Asynchronous Exception IRQ 681 Execute Command sysbus.cpu Step 682 683 # FIXME: An artificial 0x4 offset was added because Renode executes 684 # two instructions after entering exception handler with Step command 685 Current PC Should Be ${{ ${EXPECTED_PC} + 0x4 }} 686 687 [Teardown] Reset Emulation 688 689Check Protection Region Address Register Access Template 690 [Arguments] ${pl} ${reg_type} ${region_num} 691 692 Initialize Emulation pl=${pl} exec_mode=SingleStep 693 Start Emulation 694 695 IF "${reg_type}" == "Base" or "${reg_type}" == "BAR" 696 ${direct_addr_reg}= Set Variable PRBAR 697 ${selector_reg}= Set Variable PRSELR 698 ${reserved_mask}= Set Variable 0x20 699 ELSE IF "${reg_type}" == "Limit" or "${reg_type}" == "LAR" 700 ${direct_addr_reg}= Set Variable PRLAR 701 ${selector_reg}= Set Variable PRSELR 702 ${reserved_mask}= Set Variable 0x30 703 ELSE 704 Fail "Incorrect Protection Region Type" 705 END 706 ${selected_addr_reg}= Catenate SEPARATOR= ${direct_addr_reg} ${region_num} 707 IF "${pl}" == "Hypervisor" or "${pl}" == "HYP" 708 ${direct_addr_reg}= Catenate SEPARATOR= H ${direct_addr_reg} 709 ${selected_addr_reg}= Catenate SEPARATOR= H ${selected_addr_reg} 710 ${selector_reg}= Catenate SEPARATOR= H ${selector_reg} 711 END 712 Check Protection Region Address Register Access Through Selector Register ${direct_addr_reg} ${selected_addr_reg} ${selector_reg} ${region_num} ${reserved_mask} 713 Check Protection Region Address Register Access Through Direct Register ${direct_addr_reg} ${selected_addr_reg} ${selector_reg} ${region_num} ${reserved_mask} 714 715 [Teardown] Reset Emulation 716 717********************************** Test Cases ********************************* 718 719### Prerequisites 720 721Should Get Correct EL and SS on CPU Creation 722 # This platform uses `Cortex-R52` CPU - ARMv8R in AArch32 configuration 723 # We only check if EL and SS are reflected correctly on C# side, for their usage in peripherals 724 Initialize Emulation 725 726 ${ss}= Execute Command sysbus.cpu SecurityState 727 ${el}= Execute Command sysbus.cpu ExceptionLevel 728 729 Should Be Equal As Strings ${ss.split()[0].strip()} NonSecure 730 Should Be Equal As Strings ${el.split()[0].strip()} EL2_HypervisorMode 731 732Check Changing Privilege Level From Monitor 733 [Template] Check Changing Privilege Level From Monitor Template 734 [Tags] Prerequisite 735 736 FOR ${pl} IN @{AVAILABLE_PRIVILEGE_LEVELS} 737 ${pl} 738 END 739 740Check Writing To System Registers From Monitor 741 [Tags] Prerequisite 742 743 Initialize Emulation 744 Set Current System Register Value VBAR 0xCAFE0000 745 Current System Register Value Should Be VBAR 0xCAFE0000 746 747### CPU Initialization 748 749Check Privilege Level After Initialization 750 [Tags] Initialization 751 752 Initialize Emulation 753 Current Privilege Level Should Be ${HIGHEST_PRIVILEGE_LEVEL} 754 755Check CPSR Value After Initialization 756 [Tags] Initialization 757 758 Initialize Emulation 759 Check If CPSR Contains Reset Values 760 761Check PC Value After Initialization 762 [Tags] Initialization 763 764 Initialize Emulation 765 Check If Current PC Equal To RVBAR 766 767### CPU Reset 768 769Check PC Value After Reset 770 [Tags] Reset 771 772 Initialize Emulation 773 Reset CPU 774 Check If Current PC Equal To RVBAR 775 776### Hypervisor 777 778Check Access To SPSR_hyp Register 779 [Template] Check Access To SPSR_hyp Register Template 780 [Tags] Hypervisor 781 782 FOR ${pl} IN @{AVAILABLE_PRIVILEGE_LEVELS} 783 ${pl} 784 END 785 786Check Access To ELR_hyp Register 787 [Template] Check Access To ELR_hyp Template 788 [Tags] Hypervisor 789 790 User False 791 FIQ False 792 IRQ False 793 Supervisor False 794 Abort False 795 Hypervisor True 796 Undefined False 797 System False 798 799### Basic Operation 800 801Check CPSR_c Instruction Changing Privilege Level To User 802 [Template] Check CPSR_c Instruction Changing Privilege Level To User Template 803 [Tags] Basic Operation 804 805 User False 806 FIQ True 807 IRQ True 808 Supervisor True 809 Hypervisor True 810 Abort True 811 Undefined True 812 System True 813 814### Exceptions 815 816Check VBAR Register Usage By IRQ 817 [Template] Check VBAR Register Usage By IRQ Template 818 [Tags] Exceptions 819 820 User 821 FIQ 822 IRQ 823 Supervisor 824 Hypervisor 825 Abort 826 Undefined 827 System 828 829Check High Exception Vectors Usage By IRQ 830 [Template] Check High Exception Vectors Usage By IRQ Template 831 [Tags] Exceptions 832 833 User 834 FIQ 835 IRQ 836 Supervisor 837 Hypervisor 838 Abort 839 Undefined 840 System 841 842Check Debug Exceptions 843 [Template] Check Debug Exceptions Template 844 [Tags] Exceptions 845 846 BKPT 0xC 0xC 1 0x8008 847 SVC 0x8 0x0 2 0x800c 848 HVC 0x8 0x0 2 0x800c 849 850Check Asynchronous Exceptions Handling 851 [Template] Check Asynchronous Exceptions Handling Template 852 [Tags] Exceptions 853 854 FOR ${pl} IN @{AVAILABLE_PRIVILEGE_LEVELS} 855 FOR ${exception_type} IN @{AVAILABLE_ASYNCHRONOUS_EXCEPTIONS} 856 ${pl} ${exception_type} 857 END 858 END 859 860Check Synchronous Exceptions Handling 861 [Template] Check Synchronous Exceptions Handling Template 862 [Tags] Exceptions 863 864 FOR ${pl} IN @{AVAILABLE_PRIVILEGE_LEVELS} 865 FOR ${exception_type} IN @{AVAILABLE_SYNCHRONOUS_EXCEPTIONS} 866 ${pl} ${exception_type} 867 END 868 END 869 870### Address Translation Registers 871 872Check Protection Region Address Register Access 873 [Template] Check Protection Region Address Register Access Template 874 [Tags] MPU 875 876 FOR ${region_num} IN 0 7 15 877 User Base ${region_num} 878 User Limit ${region_num} 879 Hypervisor Base ${region_num} 880 Hypervisor Limit ${region_num} 881 END 882 883### Demos 884 885Run Zephyr Hello World Sample 886 [Tags] Demos 887 888 Initialize Emulation elf=${URI}/aemv8r_aarch32--zephyr-hello_world.elf-s_390996-d824c18d2044d741b7761f7ab27d3b49fae9a9e4 889 ... create_uart_tester=True 890 891 Wait For Line On Uart *** Booting Zephyr OS build ${SPACE}*** 892 Wait For Line On Uart Hello World! fvp_baser_aemv8r_aarch32 893 894Run Zephyr Synchronization Sample 895 [Tags] Demos 896 897 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-synchronization.elf-s_402972-0cd785e0ec32a0c9106dec5369ad36e4b4fb386f 898 ... create_uart_tester=True 899 900 Wait For Line On Uart Booting Zephyr OS build 901 Wait For Line On Uart thread_a: Hello World from cpu 0 on fvp_baser_aemv8r_aarch32! 902 Wait For Line On Uart thread_b: Hello World from cpu 0 on fvp_baser_aemv8r_aarch32! 903 Wait For Line On Uart thread_a: Hello World from cpu 0 on fvp_baser_aemv8r_aarch32! 904 Wait For Line On Uart thread_b: Hello World from cpu 0 on fvp_baser_aemv8r_aarch32! 905 906Run Zephyr Philosophers Sample 907 [Tags] Demos 908 909 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-philosophers.elf-s_500280-b9bbb31c64dec3f3273535be657b8e4d7ca182f9 910 ... create_uart_tester=True 911 912 Wait For Line On Uart Philosopher 0.*THINKING treatAsRegex=true 913 Wait For Line On Uart Philosopher 0.*HOLDING treatAsRegex=true 914 Wait For Line On Uart Philosopher 0.*EATING treatAsRegex=true 915 Wait For Line On Uart Philosopher 1.*THINKING treatAsRegex=true 916 Wait For Line On Uart Philosopher 1.*HOLDING treatAsRegex=true 917 Wait For Line On Uart Philosopher 1.*EATING treatAsRegex=true 918 Wait For Line On Uart Philosopher 2.*THINKING treatAsRegex=true 919 Wait For Line On Uart Philosopher 2.*HOLDING treatAsRegex=true 920 Wait For Line On Uart Philosopher 2.*EATING treatAsRegex=true 921 Wait For Line On Uart Philosopher 3.*THINKING treatAsRegex=true 922 Wait For Line On Uart Philosopher 3.*HOLDING treatAsRegex=true 923 Wait For Line On Uart Philosopher 3.*EATING treatAsRegex=true 924 Wait For Line On Uart Philosopher 4.*THINKING treatAsRegex=true 925 Wait For Line On Uart Philosopher 4.*HOLDING treatAsRegex=true 926 Wait For Line On Uart Philosopher 4.*EATING treatAsRegex=true 927 Wait For Line On Uart Philosopher 5.*THINKING treatAsRegex=true 928 Wait For Line On Uart Philosopher 5.*HOLDING treatAsRegex=true 929 Wait For Line On Uart Philosopher 5.*EATING treatAsRegex=true 930 931Run Zephyr User Space Hello World Sample 932 [Tags] Demos 933 934 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-userspace_hello_world_user.elf-s_1039836-cbc30725dd16eeb46c01b921f0c96e6a927c3669 935 ... create_uart_tester=True 936 937 Wait For Line On Uart Booting Zephyr OS build 938 Wait For Line On Uart Hello World from UserSpace! (fvp_baser_aemv8r_aarch32) 939 940Run Zephyr User Space Prod Consumer Sample 941 [Tags] Demos 942 943 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-userspace_prod_consumer.elf-s_1291928-637dbadb671ac5811ed6390b6be09447e586bf82 944 ... create_uart_tester=True 945 946 Wait For Line On Uart Booting Zephyr OS build 947 Provides zephyr-userspace_prod_consumer-after-booting 948 Wait For Line On Uart I: SUCCESS 949 950Test Resuming Zephyr User Space Prod Consumer After Deserialization 951 Requires zephyr-userspace_prod_consumer-after-booting 952 Execute Command showAnalyzer ${UART} 953 Wait For Line On Uart I: SUCCESS 954 955Run Zephyr User Space Shared Mem Sample 956 [Tags] Demos 957 958 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-userspace_shared_mem.elf-s_1096936-6da5eb0f22c62b0a23f66f68a4ba51b9ece6deff 959 ... create_uart_tester=True 960 961 Wait For Line On Uart Booting Zephyr OS build 962 Wait For Line On Uart PT Sending Message 1 963 Wait For Line On Uart ENC Thread Received Data 964 Wait For Line On Uart ENC PT MSG: PT: message to encrypt 965 Wait For Line On Uart CT Thread Received Message 966 Wait For Line On Uart CT MSG: ofttbhfspgmeqzos 967 Wait For Line On Uart PT Sending Message 1' 968 Wait For Line On Uart ENC Thread Received Data 969 Wait For Line On Uart ENC PT MSG: ofttbhfspgmeqzos 970 Wait For Line On Uart CT Thread Received Message 971 Wait For Line On Uart CT MSG: messagetoencrypt 972 973Run Zephyr Basic Sys Heap Sample 974 [Tags] Demos 975 976 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-basic_sys_heap.elf-s_433924-f490ec4c563a8f553702b7203956bf961242d91b 977 ... create_uart_tester=True 978 979 Wait For Line On Uart Booting Zephyr OS build 980 Wait For Line On Uart allocated 0, free 196, max allocated 0, heap size 256 981 Wait For Line On Uart allocated 156, free 36, max allocated 156, heap size 256 982 Wait For Line On Uart allocated 100, free 92, max allocated 156, heap size 256 983 Wait For Line On Uart allocated 0, free 196, max allocated 156, heap size 256 984 985Run Zephyr Compression LZ4 Sample 986 [Tags] Demos 987 988 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-compression_lz4.elf-s_840288-1558c5d70a6fa74ffebf6fe8a31398d29af0d087 989 ... create_uart_tester=True 990 991 Wait For Line On Uart Booting Zephyr OS build 992 Wait For Line On Uart Successfully decompressed some data 993 Wait For Line On Uart Validation done. The string we ended up with is: 994 995Run Zephyr Cpp Synchronization Sample 996 [Tags] Demos 997 998 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-cpp_cpp_synchronization.elf-s_488868-3ac689f04acc81aaf0e10b7979f12a8d66ba73d7 999 ... create_uart_tester=True 1000 1001 Wait For Line On Uart Booting Zephyr OS build 1002 Wait For Line On Uart Create semaphore 0x4e04 1003 Wait For Line On Uart Create semaphore 0x4df0 1004 Wait For Line On Uart main: Hello World! 1005 Wait For Line On Uart coop_thread_entry: Hello World! 1006 Wait For Line On Uart main: Hello World! 1007 Wait For Line On Uart coop_thread_entry: Hello World! 1008 1009Run Zephyr Kernel Condition Variables Sample 1010 [Tags] Demos 1011 1012 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-kernel_condition_variables_condvar.elf-s_478952-6ef5d598b47ef8dd8a624ffb85e4cb60fc2c6736 1013 ... create_uart_tester=True 1014 1015 Wait For Line On Uart Booting Zephyr OS build 1016 Wait For Line On Uart Main(): Waited and joined with 3 threads. Final value of count = 145. Done. 1017 1018Run Zephyr Kernel Condition Variables Simple Sample 1019 [Tags] Demos 1020 1021 Initialize Emulation elf=${URI}/fvp_baser_aemv8r_aarch32--zephyr-kernel_condition_variables_simple.elf-s_476108-e8c6ccae3076acc95f23fc3c726b4bcb8e20fff1 1022 ... create_uart_tester=True 1023 1024 Wait For Line On Uart Booting Zephyr OS build 1025 Wait For Line On Uart [thread main] done == 20 so everyone is done 1026 1027Test Reading From Overlapping MPU Regions 1028 [Tags] Exceptions 1029 1030 Initialize Emulation elf=${URI}/zephyr_pmsav8-overlapping-regions-test_fvp_baser_aemv8r_aarch32.elf-s_573792-14ad334a607d98b602f0f72522c8c22ba986b5da 1031 ... create_uart_tester=True 1032 1033 # The app will try to load from 0xCAFEBEE0 in main. It was built with an additional region in 1034 # MPU <0xCAFEB000,0xCAFEBFFF> that overlaps a default DEVICE region <0x80000000,0xFFFFFFFF>. 1035 Execute Command sysbus Tag <0xCAFEBEE0,0xCAFEBEE3> "MPU_TEST" 0xDEADCAFE 1036 1037 Wait For Line On Uart *** Booting Zephyr OS build 1038 Wait For Line On Uart Reading value from an address with overlapping MPU regions... 1039 1040 # 4 is a fault code for the Translation Fault. It doesn't have a nice log in Zephyr. 1041 # See dump_fault in arch/arm/core/aarch32/cortex_a_r/fault.c. 1042 Wait For Line On Uart DATA ABORT 1043 Wait For Line On Uart Unknown (4) 1044 1045Run Zephyr SMP Pi Sample On 4 Cores with GICv3 1046 [Tags] Demos 1047 1048 Execute Command i @platforms/cpus/cortex-r52_smp_4.repl 1049 Execute Command sysbus LoadELF ${URI}/fvp_baser_aemv8r_aarch32--zephyr-arch-smp-pi.elf-s_610540-6034d4eb76ea1b158f34bdd92ffcff2365f2c2e6 1050 1051 Execute Command showAnalyzer ${UART} 1052 Create Terminal Tester ${UART} 1053 1054 Wait For Line On Uart All 16 threads executed by 4 cores 1055 1056Run Zephyr SMP Pi Sample On 4 Cores with GICv2 1057 [Tags] Demos 1058 1059 Execute Command mach create 1060 Execute Command machine LoadPlatformDescriptionFromString ${GIC_V2_SMP} 1061 Execute Command sysbus LoadELF ${URI}/fvp_baser_aemv8r_aarch32-gicv2--zephyr-arch-smp-pi.elf-s_597400-159126f83bc84cc4c34e1f4088774ba47fc0632e 1062 1063 Execute Command showAnalyzer ${UART} 1064 Create Terminal Tester ${UART} 1065 1066 Wait For Line On Uart All 16 threads executed by 4 cores 1067
