1*** Variables *** 2${UART} sysbus.uart0 3${URI} @https://dl.antmicro.com/projects/renode 4${LINUX_PROMPT} \#${SPACE} 5 6# DTBs are embedded in Coreboot+Linux ROMs. Built with Coreboot v4.20.1, ATF v2.9.0, Linux v6.3 and Buildroot 2023.08-rc1. 7${COREBOOT_ARMv8A_ROM} ${URI}/coreboot-without-payload-armv8a.rom-s_16777216-b5c6df85cfb8d240d31fe3cd1d055a3106d2fadb 8${COREBOOT_ARMv8A_GICv2_ROM_LINUX} ${URI}/coreboot-linux-armv8a-gicv2.rom-s_67108864-fb2ff9ba59a83cc29deecaf79d4fd3a62196be8a 9${COREBOOT_ARMv8A_GICv3_ROM_LINUX} ${URI}/coreboot-linux-armv8a-gicv3.rom-s_67108864-2348c80d6b871b9ac1916dfe0fd590125559ef73 10${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX} ${URI}/coreboot-linux-armv8_2a-gicv3.rom-s_67108864-6643f8e84c2f6e9f8205d7f2d35142fad66cb959 11 12${OREBOOT_GICv2_DTB} ${URI}/aarch64-oreboot-cortex-a53-gicv2.dtb-s_1402-91c68d88d35caf827e213fed170fcda80a3a3b96 13${OREBOOT_GICv3_DTB} ${URI}/aarch64-oreboot-cortex-a53-gicv3.dtb-s_1394-6805aad03aeae232a620e6afa11d929f3a06bc95 14${OREBOOT_LINUX_BIN} ${URI}/cortex_a53-oreboot-linux-rust-shell.bin-s_67108864-9bb5a940528af703ecd716dc99e39f543e7353a7 15 16${UBOOT_DTB} ${URI}/cortex-a53-gicv2.dtb-s_1048576-2f0dd29f4be231d02cc1c99c7a85cf5c895b3b49 17${UBOOT_ELF} ${URI}/cortex-a53-u-boot.elf-s_7272248-e9dbaeaa70ddf928ec69f822180703c8729398a5 18${UBOOT_LINUX_IMAGE} ${URI}/cortex-a53-Image-s_12589568-b03715d3f08414d582a2467990dff7b4a7dd2213 19 20*** Keywords *** 21Create Machine 22 [Arguments] ${gic_version}=3 ${el2_el3_disabled}=False ${gic_security_disabled}=False ${cpu_model}=cortex-a53 23 24 Execute Command using sysbus 25 Execute Command mach create 26 ${PLATFORM} = Get File ${CURDIR}/../../platforms/cpus/cortex-a53-gicv${gic_version}.repl 27 IF "${cpu_model}" != "cortex-a53" 28 ${PLATFORM} = Replace String ${PLATFORM} cortex-a53 ${cpu_model} 29 END 30 Execute Command machine LoadPlatformDescriptionFromString """${PLATFORM}""" 31 32 IF ${el2_el3_disabled} 33 Execute Command cpu SetAvailableExceptionLevels false false 34 END 35 36 IF ${gic_security_disabled} 37 Execute Command gic DisabledSecurity true 38 END 39 40 Create Terminal Tester ${UART} defaultPauseEmulation=true 41 Execute Command showAnalyzer ${UART} 42 43Create Multicore Machine 44 Execute Command include @scripts/single-node/cortex-a53-linux.resc 45 Create Terminal Tester ${UART} 46 47Boot Linux And Login 48 # Verify that SMP works 49 Wait For Line On Uart SMP: Total of 4 processors activated includeUnfinishedLine=true 50 Wait For Prompt On Uart buildroot login: timeout=50 51 Write Line To Uart root 52 Wait For Prompt On Uart ${LINUX_PROMPT} 53 54Configure UART For Boot Logs 55 [Arguments] ${uart} 56 57 # Set UART enable bit. The reset value is 0x300. 58 Execute Command ${uart} WriteDoubleWord 0x30 0x301 59 # Set 7-bit word length to hush the warning that 5-bit WLEN is unsupported. 60 Execute Command ${uart} WriteDoubleWord 0x2c 0x40 #b10 << 5 61 62Coreboot Should Load ATF 63 Wait For Line On Uart bootblock starting 64 Wait For Line On Uart romstage starting 65 Wait For Line On Uart ramstage starting 66 Wait For Line On Uart Relocating uncompressed kernel to 0x40000000 67 Wait For Line On Uart Entry Point 0x0e0a0000 68 69ATF Should Jump To Linux 70 [Arguments] ${gic_version}=3 71 72 Wait For Line On Uart BL31: v2.9(release):v2.9.0 73 IF ${gic_version} == 2 74 Wait For Line On Uart ARM GICv2 driver initialized 75 ELSE 76 Wait For Line On Uart GICv3 with legacy support detected. 77 Wait For Line On Uart ARM GICv3 driver initialized in EL3 78 END 79 Wait For Line On Uart BL31: Preparing for EL3 exit to normal world 80 81Linux Should Print CPU Model ID 82 [Arguments] ${cpu_model}=cortex-a53 83 84 IF "${cpu_model}" == "cortex-a53" 85 ${cpu_model_id}= Set Variable 0x410fd034 86 ELSE IF "${cpu_model}" == "cortex-a75" 87 ${cpu_model_id}= Set Variable 0x413fd0a1 88 ELSE IF "${cpu_model}" == "cortex-a76" 89 ${cpu_model_id}= Set Variable 0x414fd0b1 90 ELSE IF "${cpu_model}" == "cortex-a78" 91 ${cpu_model_id}= Set Variable 0x411fd412 92 ELSE 93 Fail "No ID for the given CPU: ${cpu_model}" 94 END 95 96 Wait For Line On Uart Booting Linux on physical CPU 0x0000000000 [${cpu_model_id}] 97 98Linux Should Print GICv2 Info 99 Wait For Line On Uart GIC: Using split EOI/Deactivate mode 100 101Linux Should Print GICv3 Info 102 Wait For Line On Uart GICv3: GIC: Using split EOI/Deactivate mode 103 Wait For Line On Uart GICv3: 960 SPIs implemented 104 Wait For Line On Uart GICv3: 0 Extended SPIs implemented 105 Wait For Line On Uart Root IRQ handler: gic_handle_irq 106 Wait For Line On Uart GICv3: GICv3 features: 16 PPIs 107 Wait For Line On Uart GICv3: CPU0: found redistributor 0 region 0:0x00000000080a0000 108 109Linux Should Run Init Process 110 [Arguments] ${arch_timer_type} ${cpu_start_el} ${uart_irq} ${perfevents_counters}=False 111 ... ${squashfs}=False ${fuse}=False ${virtio_mmio_devices}=False ${check_rtc}=True 112 113 Wait For Line On Uart arch_timer: cp15 timer(s) running at 62.50MHz (${arch_timer_type}). 114 115 Wait For Line On Uart smp: Bringing up secondary CPUs ... 116 Wait For Line On Uart smp: Brought up 1 node, 1 CPU 117 Wait For Line On Uart SMP: Total of 1 processors activated. 118 Wait For Line On Uart CPU features: detected: 32-bit EL0 Support 119 Wait For Line On Uart CPU features: detected: CRC32 instructions 120 121 Wait For Line On Uart CPU: All CPU(s) started at EL${cpu_start_el} 122 123 Wait For Line On Uart Serial: AMBA PL011 UART driver 124 125 Wait For Line On Uart 9000000.pl011: ttyAMA0 at MMIO 0x9000000 (irq = ${uart_irq}, base_baud = 0) is a PL011 rev3 126 127 Wait For Line On Uart printk: console [ttyAMA0] enabled 128 129 # When comparing with the actual UART output be aware the whole log is sometimes printed again at this point. 130 131 IF ${virtio_mmio_devices} 132 # Only the first of 32 was added to the platform to check if it can be successfully used to create virtio_blk device. 133 # Initializing the remaining 31 results in 'Wrong magic value' logs. 134 Wait For Line On Uart virtio-mmio a000200.virtio_mmio: Wrong magic value 0x00000000 135 Wait For Line On uart virtio_blk virtio0: [vda] 0 512-byte logical blocks (0 B/0 B) 136 END 137 138 IF ${check_rtc} 139 Wait For Line On Uart rtc-pl031 9010000.pl031: registered as rtc0 140 # It can be the current date with 'machine RealTimeClockMode HostTimeUTC' but testing it here would be problematic. 141 Wait For Line On Uart rtc-pl031 9010000.pl031: setting system clock to 1970-01-01 142 END 143 144 Wait For Line On Uart Freeing unused kernel memory 145 146 # There are most probably problems with timer IRQs if the test fails to reach this line. 147 Wait For Line On Uart Run /init as init process 148 149Linux Should Start Rust Userspace 150 Wait For Line On Uart The words I got: [Literal("#")] 151 Wait For Line On Uart rush: #: No such file or directory (os error 2) 152 Wait For Line On Uart The words I got: [Literal("ls")] 153 Wait For Line On Uart bin \ dev \ init \ proc \ sys 154 Wait For Line On Uart The words I got: [Literal("exec")] 155 Wait For Line On Uart The words I got: [Literal("sh")] 156 Wait For Line On Uart \#> includeUnfinishedLine=true 157 158 Write Line To Uart ls 159 Wait For Line On Uart The words I got: [Literal("ls")] 160 Wait For Line On Uart bin \ dev \ init \ proc \ sys 161 162Wait For Services And Enter Shell 163 [Arguments] ${with_network}=False 164 165 Wait For Line On Uart Starting syslogd: OK 166 Wait For Line On Uart Starting klogd: OK 167 Wait For Line On Uart Running sysctl: OK 168 IF ${with_network} 169 Wait For Line On Uart Starting network: Waiting for interface eth0 to appear timeout=16 170 END 171 172 Wait For Line On Uart Welcome to Buildroot 173 Wait For Prompt On Uart buildroot login:${SPACE} 174 Write Line To Uart root 175 Wait For Prompt On Uart \#${SPACE} 176 177Shell Should Handle Basic Commands 178 # Let's only match lines that don't contain any version. 179 Write Line To Uart cat /etc/os-release 180 Wait For Line On Uart Buildroot 181 Wait For Prompt On Uart \#${SPACE} 182 183 Write Line To Uart ls -1 / 184 Wait For Line On Uart bin 185 Wait For Line On Uart dev 186 Wait For Line On Uart etc 187 Wait For Line On Uart init 188 189 ${before}= Wait For Prompt On Uart \#${SPACE} 190 191 Write Line To Uart sleep 1 192 ${after}= Wait For Prompt On Uart \#${SPACE} 193 # Timestamps are in milliseconds 194 Should Be True ${after.timestamp} - ${before.timestamp} > 1000 195 Should Be True ${after.timestamp} - ${before.timestamp} < 1050 196 197 198Test Running Coreboot With Linux And ARM Trusted Firmware 199 [Arguments] ${cpu_model} ${coreboot_rom} 200 201 Create Machine cpu_model=${cpu_model} 202 Execute Command sysbus LoadBinary ${coreboot_rom} 0x0 203 Configure UART For Boot Logs ${UART} 204 205 Coreboot Should Load ATF 206 ATF Should Jump To Linux 207 208 Linux Should Print CPU Model ID cpu_model=${cpu_model} 209 Linux Should Print GICv3 Info 210 Linux Should Run Init Process 211 ... arch_timer_type=phys 212 ... cpu_start_el=2 213 ... uart_irq=14 214 ... perfevents_counters=1 215 ... squashfs=False 216 ... fuse=True 217 218 Wait For Services And Enter Shell 219 Shell Should Handle Basic Commands 220 221*** Test Cases *** 222Test Running Coreboot Without Payload 223 Create Machine 224 Execute Command sysbus LoadBinary ${COREBOOT_ARMv8A_ROM} 0x0 225 Configure UART For Boot Logs ${UART} 226 227 Wait For Line On Uart bootblock starting 228 229 Wait For Line On Uart romstage starting 230 Wait For Line On Uart ARM64: Exception handlers installed. 231 Wait For Line On Uart RAMDETECT: Found 1024 MiB RAM 232 233 Wait For Line On Uart ramstage starting 234 # These three messages won't be shown, e.g., if accesses close to the end of RAM fail. 235 Wait For Line On Uart Timestamp - start of ramstage 236 Wait For Line On Uart Writing coreboot table 237 Wait For Line On Uart FMAP: area COREBOOT found 238 239 Wait For Line On Uart Payload not loaded. 240 241Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A53 With GICv2 242 Create Machine gic_version=2 243 Execute Command sysbus LoadBinary ${COREBOOT_ARMv8A_GICv2_ROM_LINUX} 0x0 244 Configure UART For Boot Logs ${UART} 245 246 Coreboot Should Load ATF 247 ATF Should Jump To Linux gic_version=2 248 249 Linux Should Print CPU Model ID 250 Linux Should Print GICv2 Info 251 Linux Should Run Init Process 252 ... arch_timer_type=phys 253 ... cpu_start_el=2 254 ... uart_irq=14 255 256 Wait For Services And Enter Shell 257 Shell Should Handle Basic Commands 258 259Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A53 260 Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a53 ${COREBOOT_ARMv8A_GICv3_ROM_LINUX} 261 262Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A75 263 Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a75 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX} 264 265Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A76 266 Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a76 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX} 267 268Test Running Coreboot With Linux And ARM Trusted Firmware On Cortex-A78 269 Test Running Coreboot With Linux And ARM Trusted Firmware cortex-a78 ${COREBOOT_ARMv8_2A_GICv3_ROM_LINUX} 270 271Test Running Oreboot With Linux And Rust Shell With GICv2 272 Create Machine gic_version=2 el2_el3_disabled=True gic_security_disabled=True 273 274 Execute Command sysbus LoadBinary ${OREBOOT_GICv2_DTB} 0x40000000 275 Execute Command sysbus LoadBinary ${OREBOOT_LINUX_BIN} 0x0 276 277 Configure UART For Boot Logs ${UART} 278 Execute Command cpu.timer CounterFrequencyRegister 62500000 279 280 Wait For Line On Uart Welcome to oreboot 281 Wait For Line On Uart Not in EL3, jumping to payload 282 283 Linux Should Print CPU Model ID 284 285 # There are no details on GIC version. 286 Wait For Line On Uart NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 287 Wait For Line On Uart Root IRQ handler: gic_handle_irq 288 289 Linux Should Run Init Process 290 ... arch_timer_type=virt 291 ... cpu_start_el=1 292 ... uart_irq=13 293 ... check_rtc=False 294 295 Linux Should Start Rust Userspace 296 297Test Running Oreboot With Linux And Rust Shell With GICv3 298 Create Machine el2_el3_disabled=True gic_security_disabled=True 299 300 Execute Command sysbus LoadBinary ${OREBOOT_GICv3_DTB} 0x40000000 301 Execute Command sysbus LoadBinary ${OREBOOT_LINUX_BIN} 0x0 302 303 Configure UART For Boot Logs ${UART} 304 Execute Command cpu.timer CounterFrequencyRegister 62500000 305 306 Wait For Line On Uart Welcome to oreboot 307 Wait For Line On Uart Not in EL3, jumping to payload 308 309 Linux Should Print CPU Model ID 310 311 Wait For Line On Uart NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0 312 Wait For Line On Uart GICv3: 960 SPIs implemented 313 Wait For Line On Uart Root IRQ handler: gic_handle_irq 314 315 Linux Should Run Init Process 316 ... arch_timer_type=virt 317 ... cpu_start_el=1 318 ... uart_irq=13 319 ... check_rtc=False 320 321 Linux Should Start Rust Userspace 322 323Test Running U-Boot With Linux 324 # U-Boot doesn't properly support GIC Security Extensions. 325 Create Machine gic_version=2 gic_security_disabled=True 326 327 # DeviceTree contains 32 virtio_blk/virtio_mmio devices at 0x0a000000, 0x0a000200, ..., 0x0a003e00 but 328 # let's at least add one to check if it can be properly initialized. Initializing others won't succeed. 329 Execute Command machine LoadPlatformDescriptionFromString "virtio0: Storage.VirtIOBlockDevice @ sysbus 0x0a000000" 330 331 Execute Command sysbus LoadELF ${UBOOT_ELF} 332 Execute Command sysbus LoadBinary ${UBOOT_DTB} 0x40000000 333 Execute Command sysbus LoadBinary ${UBOOT_LINUX_IMAGE} 0x40400000 334 335 # In U-Boot, this register is expected to be configured by a previous bootloader. 336 Execute Command cpu.timer CounterFrequencyRegister 62500000 337 338 Wait For Line On Uart U-Boot 2023.01 339 Wait For Line On Uart Hit any key to stop autoboot includeUnfinishedLine=true 340 Write Line To Uart 341 Write Line To Uart setenv bootargs \"console=ttyAMA0 earlycon\"; booti 0x40400000 - \${fdtcontroladdr} 342 343 Wait For Line On Uart Starting kernel ... 344 345 Linux Should Print CPU Model ID 346 Linux Should Print GICv2 Info 347 Linux Should Run Init Process 348 ... arch_timer_type=phys 349 ... cpu_start_el=2 350 ... uart_irq=48 351 ... virtio_mmio_devices=True 352 353 Wait For Services And Enter Shell with_network=True 354 Shell Should Handle Basic Commands 355 356Should Boot And Login 357 Create Multicore Machine 358 359 Boot Linux And Login 360 361 # Check if we see other CPUs 362 Write Line To Uart nproc 363 Wait For Line On Uart 4
