1*** Keywords *** 2Create Machine 3 [Arguments] ${elf_file} 4 Execute Command using sysbus 5 Execute Command mach create 6 Execute Command machine LoadPlatformDescription @platforms/cpus/cortex-r8.repl 7 8 Execute Command sysbus LoadELF @${elf_file} 9 Create Terminal Tester sysbus.uart1 timeout=5 defaultPauseEmulation=true 10 11Run Hello World 12 [Arguments] ${elf_file} ${board_name} 13 Create Machine ${elf_file} 14 Start Emulation 15 Wait For Line On Uart *** Booting Zephyr OS build 16 Wait For Line On Uart Hello World! ${board_name} 17 18Run Philosophers 19 [Arguments] ${elf_file} 20 Create Machine ${elf_file} 21 Start Emulation 22 Wait For Line On Uart Philosopher 5.*THINKING treatAsRegex=true 23 Wait For Line On Uart Philosopher 5.*HOLDING treatAsRegex=true 24 Wait For Line On Uart Philosopher 5.*EATING treatAsRegex=true 25 26Run Shell Module 27 [Arguments] ${elf_file} 28 Create Machine ${elf_file} 29 Start Emulation 30 Wait For Prompt On Uart uart:~$ 31 Write Line To Uart 32 Wait For Prompt On Uart uart:~$ 33 Write Line To Uart demo board 34 Wait For Line On Uart kv260_r8 35 36Remap Exception Vector 37 [Arguments] ${cpu} ${remapped_vector_base_addr} 38 Execute Command ${cpu} ExceptionVectorAddress ${remapped_vector_base_addr} 39 Wait For Log Entry ${cpu}: Successfully set ExceptionVectorAddress to ${remapped_vector_base_addr} on a CPU supporting neither VBAR nor VTOR; such customization might not be possible on hardware. 40 41Verify Exception Vector Base Address 42 [Arguments] ${cpu} ${expected_vector_base_addr} 43 44 ${expected_vector_udef_addr} Set Variable ${{ ${expected_vector_base_addr} + 0x4 }} 45 46 # Let's make the first instruction invalid and try to execute it. It isn't placed at 0x0 47 # because the undefined instruction handler's offset is 0x4. With the instruction placed 48 # at 0x0 distinguishing between between 0x4 being a result of a single step and jumping 49 # to the undefined instruction handler wouldn't be possible. 50 ${program_start}= Set Variable 0x1000 51 Execute Command sysbus WriteDoubleWord ${program_start} 0xf1010200 52 Execute Command ${cpu} PC ${program_start} 53 54 # The next PC is expected to be the undefined instruction handler in the remapped vector. 55 Execute Command ${cpu} Step 56 Verify PC ${cpu} ${expected_vector_udef_addr} 57 58Verify PC 59 [Arguments] ${cpu} ${expected_value} 60 61 ${pc}= Execute Command ${cpu} PC 62 Should Be Equal As Integers ${pc} ${expected_value} 63 64*** Test Cases *** 65Should Run Hello World 3.6.0 66 Run Hello World https://dl.antmicro.com/projects/renode/zephyr-3.6.0--samples_hello_world--kv260_r8.elf-s_414440-9d6b2002dffe7938f055fa7963884c6b0a578f65 kv260_r8/zynqmp_rpu_r8 67 68Should Run Philosophers 3.6.0 69 Run Philosophers https://dl.antmicro.com/projects/renode/zephyr-3.6.0--samples_philosophers--kv260_r8.elf-s_459704-7ede6e5bb6dec1e16e83c23ea5f97279302c3bbb 70 71Should Run Shell Module 3.6.0 72 Run Shell Module https://dl.antmicro.com/projects/renode/zephyr-3.6.0--samples_subsys_shell_shell_module--kv260_r8.elf-s_1340080-84f1f45dafb5b55727b8a8ae19636f2464339489 73 74Should Run Hello World 3.4.0 75 Run Hello World https://dl.antmicro.com/projects/renode/zephyr-3.4.0--samples_hello_world--kv260_r8.elf-s_373384-c63ba3672f7e6457c6aedc178068b7e5784a5b0b board_kv260_r8 76 77Should Run Philosophers 3.4.0 78 Run Philosophers https://dl.antmicro.com/projects/renode/zephyr-3.4.0--samples_philosophers--kv260_r8.elf-s_490412-601fea129a84738c54aeefb92092ca6d6e1f8119 79 80Should Run Shell Module 3.4.0 81 Run Shell Module https://dl.antmicro.com/projects/renode/zephyr-3.4.0--samples_subsys_shell_shell_module--kv260_r8.elf-s_1276220-ad5d7f3f1f7c813135c874bd77e1e25cc4510298 82 83Test Remapping Exception Vector 84 ${default_vector_base} Set Variable 0x0 85 ${remapped_vector_base_cpu0} Set Variable 0x1000000 86 ${remapped_vector_base_cpu2} Set Variable 0x1234560 87 88 Execute Command using sysbus 89 Execute Command mach create 90 Execute Command machine LoadPlatformDescription @platforms/cpus/cortex-r8_smp.repl 91 Create Log Tester 1 92 93 # Prevent starting other CPUs when stepping one of them. 94 FOR ${cpu_idx} IN RANGE 4 95 Execute Command cpu${cpu_idx} ExecutionMode SingleStep 96 END 97 98 # Let's remap exception vector for cpu0 and cpu2. 99 Remap Exception Vector cpu0 ${remapped_vector_base_cpu0} 100 Remap Exception Vector cpu2 ${remapped_vector_base_cpu2} 101 102 # Verify exception vectors, it should be a default for other CPUs. 103 Verify Exception Vector Base Address cpu0 ${remapped_vector_base_cpu0} 104 Verify Exception Vector Base Address cpu1 ${default_vector_base} 105 Verify Exception Vector Base Address cpu2 ${remapped_vector_base_cpu2} 106 Verify Exception Vector Base Address cpu3 ${default_vector_base} 107