1$name?="Vegaboard-RI5CY"
2
3using sysbus
4mach create $name
5machine LoadPlatformDescription @platforms/cpus/ri5cy.repl
6
7$pcc_mock="""
8if request.isInit: lastVal = 0x80000000
9if request.isRead: request.value = lastVal
10if request.isWrite: lastVal = request.value
11"""
12
13$bin?=@https://dl.antmicro.com/projects/renode/vegaboard--zephyr_shell.elf-s_1000428-46ce2752ebea346c8d232ab4e4f8d489999488af
14
15showAnalyzer lpuart0
16
17sysbus LoadELF $bin
18
19sysbus Tag <0x4004f000 0x1e4> "INTMUX0: Interrupt Multiplexer 0"
20sysbus Tag <0x4002b000 0x204> "PCC0: Peripheral Clock Controller 0"
21sysbus Tag <0x41027000 0x204> "PCC1: Peripheral Clock Controller 1"
22
23# Clock Status Register
24machine PyDevFromString """
25if request.isInit:
26    ctr = 0
27else:
28    if ctr > 0:
29        request.value = 0x3000001
30    else:
31        request.value = 0x2000000
32    ctr += 1
33""" 0x4002c010 0x4 True
34
35# Peripheral Clock Controller 0 TPM2
36machine PyDevFromString $pcc_mock 0x4002b0dc 0x4 True
37
38# Peripheral Clock Controller 0 PORTA
39machine PyDevFromString $pcc_mock 0x4002b118 0x4 True
40
41# Peripheral Clock Controller 0 PORTB
42machine PyDevFromString $pcc_mock 0x4002b11c 0x4 True
43
44# Peripheral Clock Controller 0 PORTC
45machine PyDevFromString $pcc_mock 0x4002b120 0x4 True
46
47# Peripheral Clock Controller 0 PORTD
48machine PyDevFromString $pcc_mock 0x4002b124 0x4 True
49
50# Peripheral Clock Controller 0 unmapped
51machine PyDevFromString $pcc_mock 0x4002b13c 0x4 True
52
53# Peripheral Clock Controller 0 LPUART0
54machine PyDevFromString $pcc_mock 0x4002b108 0x4 True
55
56# Peripheral Clock Controller 1 PORTE
57machine PyDevFromString $pcc_mock 0x410270dc 0x4 True
58
59# Peripheral Clock Controller 1 GPIOE
60machine PyDevFromString $pcc_mock 0x4102703c 0x4 True
61
62# Slow IRC Control Status Register
63sysbus Tag <0x4002c200 4> "SIRCCSR" 0xFFFFFFFF
64
65# Fast IRC Control Status Register
66sysbus Tag <0x4002c300 4> "FIRCCSR" 0xFFFFFFFF
67
68# Fast IRC Divider Register
69sysbus Tag <0x4002c304 4> "FIRCDIV" 0x00010101  # Divide by 1
70
71# Low Power FLL Control Status Register
72sysbus Tag <0x4002c500 4> "LPFFLCSR" 0xFFFFFFFF
73
74# Slow IRC Configuration Register: configured as high range clock (8 MHz)
75sysbus Tag <0x4002c208 4> "SIRCFFG" 0x1
76
77# INTMUX0 Channel0 IRQ Source Register
78# the value is hardcoded to the one corresponding to lptmr0
79sysbus Tag <0x4004f004 4> "intmux0_channel0_source" 0xdc
80
81# EVENT0: Clear Interrupt Pending Register
82# this is silenced because CPU writes 1 to this register
83# in order to clear interrupt in INTMUX0; since we don't
84# have this peripheral yet, it would generate a lot of
85# warnings in log; this should be removed once INTMUX
86# peripheral is merged
87sysbus SilenceRange <0xe004100c 4>
88