1:name: OpenTitan Earlgrey
2:description: This script runs hello world example on OpenTitan Earl Grey at commit f243e6802143374741739d2c164c4f2f61697669
3
4$name?="EarlGrey"
5
6using sysbus
7mach create $name
8machine LoadPlatformDescription @platforms/cpus/opentitan-earlgrey-cw310.repl
9
10showAnalyzer sysbus.uart0
11
12$boot?=@https://dl.antmicro.com/projects/renode/test_rom_fpga_cw310.elf-s_447072-1cdfd7b2a98b0c09f158d8267c5e9fbbf34dd33b
13$boot_vmem?=@https://dl.antmicro.com/projects/renode/test_rom_fpga_cw310.39.scr.vmem-s_103772-d3a8f17879eedbcbf18e554bfd7871ccd992414e
14$otp_vmem?=@https://dl.antmicro.com/projects/renode/open_titan-earlgrey--otp-img.24.vmem-s_44628-e17dede45d7e0509540343e52fe6fce1454c5339
15$bin?=@https://dl.antmicro.com/projects/renode/open_titan-earlgrey--hello_world_fpga_cw310.elf-s_376640-48103e09bc133bb823f56b2768ae9f55fc0cc01e
16
17# NMI vector address for Ibex CPU is relative to MTVEC value: https://github.com/lowRISC/ibex/blob/97df7a5b10a1baf25633771a385aff59cea8b0fa/doc/03_reference/exception_interrupts.rst?plain=1#L57
18# MTVEC is set by a bootloader and is not known upfront. Used test rom sets MTVEC to address 0x20000401 (vectored interrupt handler) and we hardcode NMI vector address below.
19cpu0 NMIVectorAddress 0x2000047c
20cpu0 NMIVectorLength 1
21
22macro reset
23"""
24    sysbus LoadELF $bin
25    sysbus LoadELF $boot
26    rom_ctrl LoadVmem $boot_vmem
27    otp_ctrl LoadVmem $otp_vmem
28"""
29
30runMacro $reset
31
32