1 //
2 // Copyright (c) 2010-2024 Antmicro
3 //
4 // This file is licensed under the MIT License.
5 // Full license text is available in 'licenses/MIT.txt'.
6 //
7 
8 using System.Linq;
9 using System.Text;
10 using Antmicro.Renode.Core;
11 using Antmicro.Renode.Logging;
12 using Antmicro.Renode.Peripherals.Bus;
13 
14 namespace Antmicro.Renode.Peripherals.CPU
15 {
16     public class SampleStateAwarePeripheral : IDoubleWordPeripheral, IKnownSize
17     {
SampleStateAwarePeripheral(IMachine machine, long size)18         public SampleStateAwarePeripheral(IMachine machine, long size)
19         {
20             this.size = size;
21             sysbus = machine.GetSystemBus(this);
22         }
23 
Reset()24         public void Reset()
25         {
26         }
27 
ReadDoubleWord(long offset)28         public uint ReadDoubleWord(long offset)
29         {
30             if(!sysbus.TryGetCurrentContextState<CortexM.ContextState>(out var initiator, out var cpuState))
31             {
32                 this.WarningLog("No context");
33                 return 0;
34             }
35             var peripheralName = initiator.GetName().Split('.')[1];
36             bool privileged = (bool)cpuState.Privileged, cpuSecure = (bool)cpuState.CpuSecure, attributionSecure = (bool)cpuState.AttributionSecure;
37             this.WarningLog("Read from context: {0} state.Privileged: {1}, state.CpuSecure: {2}, state.AttributionSecure: {3}", peripheralName, privileged, cpuSecure, attributionSecure);
38             var peripheralNameBytes = Encoding.UTF8.GetBytes(peripheralName).Take(3).Aggregate(0U, (v, b) => (v << 8) | b);
39             return (peripheralNameBytes << 8) | ((privileged ? 1u : 0) << 0) | ((cpuSecure ? 1u : 0) << 1) | ((attributionSecure ? 1u : 0) << 2);
40         }
41 
WriteDoubleWord(long offset, uint value)42         public void WriteDoubleWord(long offset, uint value)
43         {
44         }
45 
46         public long Size => size;
47 
48         private readonly long size;
49         private readonly IBusController sysbus;
50     }
51 }
52