1// instram0, dataram0 and dataram1 are defined in 'core-isa.h'.
2instram0: Memory.MappedMemory @ sysbus 0x40000000
3    size: 0x20000
4
5dataram0: Memory.MappedMemory @ sysbus 0x3FFE0000
6    size: 0x20000
7
8dataram1: Memory.MappedMemory @ sysbus 0x3FFC0000
9    size: 0x20000
10
11// The reset vector points to 0x50000000.
12rom: Memory.MappedMemory @ sysbus 0x50000000
13    size: 0x4000000
14
15ram: Memory.MappedMemory @ sysbus 0x60000000
16    size: 0x8000000
17
18cpu: CPU.Xtensa @ sysbus
19    cpuType: "sample_controller"
20    frequency: 100000000
21
22uartSemihosting: UART.SemihostingUart @ cpu
23
24