1program: Memory.MappedMemory @ sysbus 0x0
2    size: 0x00040000
3
4
5flexnvm: Memory.MappedMemory @ sysbus 0x10000000
6    size: 0x00008000
7
8
9// Should be 0x800 + 0x80 for CSE_PRAM, but internal
10// limitations require us to align regions to 0x400
11flexram: Memory.MappedMemory @ sysbus 0x14000000
12    size: 0x00000800
13
14
15sram_l: Memory.MappedMemory @ sysbus 0x1C000000
16    size: 0x4000000
17
18
19sram_u: Memory.MappedMemory @ sysbus 0x20000000
20    size: 0x5800
21
22
23nvic: IRQControllers.NVIC @ sysbus 0xE000E000
24    priorityMask: 0xF0
25    systickFrequency: 72000000
26    IRQ -> cpu@0
27
28
29cpu: CPU.CortexM @ sysbus
30    cpuType: "cortex-m0+"
31    nvic: nvic
32
33
34dwt: Miscellaneous.DWT @ sysbus 0xE0001000
35    frequency: 48000000
36
37
38lpspi0: SPI.IMXRT_LPSPI @ sysbus 0x4002C000
39    -> nvic@26
40
41
42lpspi1: SPI.IMXRT_LPSPI @ sysbus 0x4002D000
43    -> nvic@27
44
45
46lpuart0: UART.NXP_LPUART @ sysbus 0x4006A000
47    IRQ -> nvic@31
48
49
50lpuart1: UART.NXP_LPUART @ sysbus 0x4006B000
51    IRQ -> nvic@30
52
53
54can0_mcr: Python.PythonPeripheral @ sysbus 0x40024000
55    size: 0x4
56    initable: true
57    filename: "scripts/pydev/flipflop.py"
58
59
60lpit: Timers.S32K_LPIT @ sysbus 0x40037000
61    frequency: 5000
62    IRQ -> nvic@20
63
64
65lptmr: Timers.S32K_LPTMR @ sysbus 0x40040000
66    -> nvic@8
67    frequency: 80000000
68
69
70portGPIO: Miscellaneous.CombinedInput
71    numberOfInputs: 5
72    -> nvic@9
73
74
75portA: GPIOPort.NXPGPIOPort @ {
76        sysbus new Bus.BusMultiRegistration { address: 0x400FF000; size: 0x40; region: "gpio" };
77        sysbus new Bus.BusMultiRegistration { address: 0x40049000; size: 0xD0; region: "port" }
78    }
79    numberOfPins: 12
80    -> portGPIO@0
81
82
83portB: GPIOPort.NXPGPIOPort @ {
84    sysbus new Bus.BusMultiRegistration { address: 0x400FF040; size: 0x40; region: "gpio" };
85    sysbus new Bus.BusMultiRegistration { address: 0x4004A000; size: 0xD0; region: "port" }}
86    numberOfPins: 10
87    -> portGPIO@1
88
89
90portC: GPIOPort.NXPGPIOPort @ {
91    sysbus new Bus.BusMultiRegistration { address: 0x400FF080; size: 0x40; region: "gpio" };
92    sysbus new Bus.BusMultiRegistration { address: 0x4004B000; size: 0xD0; region: "port" }}
93    numberOfPins: 14
94    -> portGPIO@2
95
96
97portD: GPIOPort.NXPGPIOPort @ {
98    sysbus new Bus.BusMultiRegistration { address: 0x400FF0C0; size: 0x40; region: "gpio" };
99    sysbus new Bus.BusMultiRegistration { address: 0x4004C000; size: 0xD0; region: "port" }}
100    numberOfPins: 10
101    -> portGPIO@3
102
103
104portE: GPIOPort.NXPGPIOPort @ {
105    sysbus new Bus.BusMultiRegistration { address: 0x400FF100; size: 0x40; region: "gpio" };
106    sysbus new Bus.BusMultiRegistration { address: 0x4004D000; size: 0xD0; region: "port" }}
107    numberOfPins: 12
108    -> portGPIO@4
109
110
111scg: Miscellaneous.S32K_SCG @ sysbus 0x40064000
112
113
114sysbus:
115    init:
116        ApplySVD @https://dl.antmicro.com/projects/renode/S32K118.svd-s_4356973-8b6f35da75a942816cd0d662d28a690e8b3484e3
117        Tag <0x40024000, 0x40024003> "CAN0:MCR" 0x0
118        Tag <0x40038000, 0x40038003> "FTM0:SC" 0x1
119        Tag <0x400650DC, 0x400650DF> "PPC:PPC_LPIT" 0xF9FFFFFF
120        Tag <0x400651A8, 0x400651AB> "PPC:PPC_LPUART0" 0xF9FFFFFF
121        Tag <0x400651AC, 0x400651AF> "PPC:PPC_UART" 0xF9FFFFFF
122