1// This platform's configuration is based on:
2// https://github.com/zephyrproject-rtos/zephyr/blob/master/dts/riscv/riscv32-litex-vexriscv.dtsi
3
4ram: Memory.MappedMemory @ {
5        sysbus 0x40000000;
6        sysbus 0xc0000000 // shadow
7    }
8    size: 0x10000000
9
10cpu: CPU.VexRiscv @ sysbus
11    cpuType: "rv32imac_zicsr_zifencei"
12
13uart: UART.LiteX_UART @ {
14        sysbus 0x60001800;
15        sysbus 0xE0001800 // shadow
16    }
17    -> cpu@2
18
19spi: SPI.LiteX_SPI @ {
20        sysbus 0x60002000;
21        sysbus 0xE0002000 // shadow
22    }
23
24timer0: Timers.LiteX_Timer @ {
25        sysbus 0x60002800;
26        sysbus 0xE0002800 // shadow
27    }
28    frequency: 100000000
29    -> cpu@1
30
31gpio_out: GPIOPort.LiteX_GPIO @ {
32        sysbus 0x60005800;
33        sysbus 0xE0005800 // shadow
34    }
35    type: Type.Out
36
37gpio_in: GPIOPort.LiteX_GPIO @ {
38        sysbus 0x60006000;
39        sysbus 0xE0006000 // shadow
40    }
41    type: Type.In
42
43eth: Network.LiteX_Ethernet @ {
44        sysbus 0x60009800;
45        sysbus 0xE0009800; // shadow
46
47        sysbus new Bus.BusMultiRegistration { address: 0x30000000; size: 0x2000; region: "buffer" };
48        sysbus new Bus.BusMultiRegistration { address: 0xB0000000; size: 0x2000; region: "buffer" }; // shadow
49
50        sysbus new Bus.BusMultiRegistration { address: 0x60009000; size: 0x800; region: "phy" };
51        sysbus new Bus.BusMultiRegistration { address: 0xe0009000; size: 0x800; region: "phy" } // shadow
52    }
53
54sysbus:
55    init:
56        Tag <0xE0003800 0x100> "DNA"
57        Tag <0xE0005000 0x100> "I2C"
58        Tag <0xE0006800 0x100> "PRBS RNG"
59        Tag <0xE0007000 0x100> "PWM"
60