1 /******************************************************** 2 * 3 * Warning! 4 * This file was generated automatically. 5 * Please do not edit. Changes should be made in the 6 * appropriate *.tt file. 7 * 8 */ 9 using System; 10 using System.Linq; 11 using System.Collections.Generic; 12 using Antmicro.Renode.Peripherals.CPU.Registers; 13 using Antmicro.Renode.Utilities.Binding; 14 using Antmicro.Renode.Exceptions; 15 16 namespace Antmicro.Renode.Peripherals.CPU 17 { 18 public partial class Xtensa 19 { SetRegister(int register, RegisterValue value)20 public override void SetRegister(int register, RegisterValue value) 21 { 22 if(!mapping.TryGetValue((XtensaRegisters)register, out var r)) 23 { 24 throw new RecoverableException($"Wrong register index: {register}"); 25 } 26 if(r.IsReadonly) 27 { 28 throw new RecoverableException($"The '{(XtensaRegisters)register}' register is read-only."); 29 } 30 31 SetRegisterValue32(r.Index, checked((uint)value)); 32 } 33 GetRegister(int register)34 public override RegisterValue GetRegister(int register) 35 { 36 if(!mapping.TryGetValue((XtensaRegisters)register, out var r)) 37 { 38 throw new RecoverableException($"Wrong register index: {register}"); 39 } 40 return GetRegisterValue32(r.Index); 41 } 42 GetRegisters()43 public override IEnumerable<CPURegister> GetRegisters() 44 { 45 return mapping.Values.OrderBy(x => x.Index); 46 } 47 48 [Register] 49 public override RegisterValue PC 50 { 51 get 52 { 53 return GetRegisterValue32((int)XtensaRegisters.PC); 54 } 55 set 56 { 57 SetRegisterValue32((int)XtensaRegisters.PC, value); 58 } 59 } 60 [Register] 61 public RegisterValue SAR 62 { 63 get 64 { 65 return GetRegisterValue32((int)XtensaRegisters.SAR); 66 } 67 set 68 { 69 SetRegisterValue32((int)XtensaRegisters.SAR, value); 70 } 71 } 72 [Register] 73 public RegisterValue WINDOWBASE 74 { 75 get 76 { 77 return GetRegisterValue32((int)XtensaRegisters.WINDOWBASE); 78 } 79 set 80 { 81 SetRegisterValue32((int)XtensaRegisters.WINDOWBASE, value); 82 } 83 } 84 [Register] 85 public RegisterValue WINDOWSTART 86 { 87 get 88 { 89 return GetRegisterValue32((int)XtensaRegisters.WINDOWSTART); 90 } 91 set 92 { 93 SetRegisterValue32((int)XtensaRegisters.WINDOWSTART, value); 94 } 95 } 96 [Register] 97 public RegisterValue PS 98 { 99 get 100 { 101 return GetRegisterValue32((int)XtensaRegisters.PS); 102 } 103 set 104 { 105 SetRegisterValue32((int)XtensaRegisters.PS, value); 106 } 107 } 108 [Register] 109 public RegisterValue EXPSTATE 110 { 111 get 112 { 113 return GetRegisterValue32((int)XtensaRegisters.EXPSTATE); 114 } 115 set 116 { 117 SetRegisterValue32((int)XtensaRegisters.EXPSTATE, value); 118 } 119 } 120 [Register] 121 public RegisterValue MMID 122 { 123 get 124 { 125 return GetRegisterValue32((int)XtensaRegisters.MMID); 126 } 127 set 128 { 129 SetRegisterValue32((int)XtensaRegisters.MMID, value); 130 } 131 } 132 [Register] 133 public RegisterValue IBREAKENABLE 134 { 135 get 136 { 137 return GetRegisterValue32((int)XtensaRegisters.IBREAKENABLE); 138 } 139 set 140 { 141 SetRegisterValue32((int)XtensaRegisters.IBREAKENABLE, value); 142 } 143 } 144 [Register] 145 public RegisterValue ATOMCTL 146 { 147 get 148 { 149 return GetRegisterValue32((int)XtensaRegisters.ATOMCTL); 150 } 151 set 152 { 153 SetRegisterValue32((int)XtensaRegisters.ATOMCTL, value); 154 } 155 } 156 [Register] 157 public RegisterValue DDR 158 { 159 get 160 { 161 return GetRegisterValue32((int)XtensaRegisters.DDR); 162 } 163 set 164 { 165 SetRegisterValue32((int)XtensaRegisters.DDR, value); 166 } 167 } 168 [Register] 169 public RegisterValue DEPC 170 { 171 get 172 { 173 return GetRegisterValue32((int)XtensaRegisters.DEPC); 174 } 175 set 176 { 177 SetRegisterValue32((int)XtensaRegisters.DEPC, value); 178 } 179 } 180 [Register] 181 public RegisterValue INTERRUPT 182 { 183 get 184 { 185 return GetRegisterValue32((int)XtensaRegisters.INTERRUPT); 186 } 187 set 188 { 189 SetRegisterValue32((int)XtensaRegisters.INTERRUPT, value); 190 } 191 } 192 [Register] 193 public RegisterValue INTSET 194 { 195 get 196 { 197 return GetRegisterValue32((int)XtensaRegisters.INTSET); 198 } 199 set 200 { 201 SetRegisterValue32((int)XtensaRegisters.INTSET, value); 202 } 203 } 204 [Register] 205 public RegisterValue INTCLEAR 206 { 207 get 208 { 209 return GetRegisterValue32((int)XtensaRegisters.INTCLEAR); 210 } 211 set 212 { 213 SetRegisterValue32((int)XtensaRegisters.INTCLEAR, value); 214 } 215 } 216 [Register] 217 public RegisterValue INTENABLE 218 { 219 get 220 { 221 return GetRegisterValue32((int)XtensaRegisters.INTENABLE); 222 } 223 set 224 { 225 SetRegisterValue32((int)XtensaRegisters.INTENABLE, value); 226 } 227 } 228 [Register] 229 public RegisterValue VECBASE 230 { 231 get 232 { 233 return GetRegisterValue32((int)XtensaRegisters.VECBASE); 234 } 235 set 236 { 237 SetRegisterValue32((int)XtensaRegisters.VECBASE, value); 238 } 239 } 240 [Register] 241 public RegisterValue EXCCAUSE 242 { 243 get 244 { 245 return GetRegisterValue32((int)XtensaRegisters.EXCCAUSE); 246 } 247 set 248 { 249 SetRegisterValue32((int)XtensaRegisters.EXCCAUSE, value); 250 } 251 } 252 [Register] 253 public RegisterValue DEBUGCAUSE 254 { 255 get 256 { 257 return GetRegisterValue32((int)XtensaRegisters.DEBUGCAUSE); 258 } 259 set 260 { 261 SetRegisterValue32((int)XtensaRegisters.DEBUGCAUSE, value); 262 } 263 } 264 [Register] 265 public RegisterValue CCOUNT 266 { 267 get 268 { 269 return GetRegisterValue32((int)XtensaRegisters.CCOUNT); 270 } 271 set 272 { 273 SetRegisterValue32((int)XtensaRegisters.CCOUNT, value); 274 } 275 } 276 [Register] 277 public RegisterValue PRID 278 { 279 get 280 { 281 return GetRegisterValue32((int)XtensaRegisters.PRID); 282 } 283 set 284 { 285 SetRegisterValue32((int)XtensaRegisters.PRID, value); 286 } 287 } 288 [Register] 289 public RegisterValue ICOUNT 290 { 291 get 292 { 293 return GetRegisterValue32((int)XtensaRegisters.ICOUNT); 294 } 295 set 296 { 297 SetRegisterValue32((int)XtensaRegisters.ICOUNT, value); 298 } 299 } 300 [Register] 301 public RegisterValue ICOUNTLEVEL 302 { 303 get 304 { 305 return GetRegisterValue32((int)XtensaRegisters.ICOUNTLEVEL); 306 } 307 set 308 { 309 SetRegisterValue32((int)XtensaRegisters.ICOUNTLEVEL, value); 310 } 311 } 312 [Register] 313 public RegisterValue EXCVADDR 314 { 315 get 316 { 317 return GetRegisterValue32((int)XtensaRegisters.EXCVADDR); 318 } 319 set 320 { 321 SetRegisterValue32((int)XtensaRegisters.EXCVADDR, value); 322 } 323 } 324 [Register] 325 public RegisterValue PSINTLEVEL 326 { 327 get 328 { 329 return GetRegisterValue32((int)XtensaRegisters.PSINTLEVEL); 330 } 331 set 332 { 333 SetRegisterValue32((int)XtensaRegisters.PSINTLEVEL, value); 334 } 335 } 336 [Register] 337 public RegisterValue PSUM 338 { 339 get 340 { 341 return GetRegisterValue32((int)XtensaRegisters.PSUM); 342 } 343 set 344 { 345 SetRegisterValue32((int)XtensaRegisters.PSUM, value); 346 } 347 } 348 [Register] 349 public RegisterValue PSWOE 350 { 351 get 352 { 353 return GetRegisterValue32((int)XtensaRegisters.PSWOE); 354 } 355 set 356 { 357 SetRegisterValue32((int)XtensaRegisters.PSWOE, value); 358 } 359 } 360 [Register] 361 public RegisterValue PSEXCM 362 { 363 get 364 { 365 return GetRegisterValue32((int)XtensaRegisters.PSEXCM); 366 } 367 set 368 { 369 SetRegisterValue32((int)XtensaRegisters.PSEXCM, value); 370 } 371 } 372 [Register] 373 public RegisterValue PSCALLINC 374 { 375 get 376 { 377 return GetRegisterValue32((int)XtensaRegisters.PSCALLINC); 378 } 379 set 380 { 381 SetRegisterValue32((int)XtensaRegisters.PSCALLINC, value); 382 } 383 } 384 [Register] 385 public RegisterValue PSOWB 386 { 387 get 388 { 389 return GetRegisterValue32((int)XtensaRegisters.PSOWB); 390 } 391 set 392 { 393 SetRegisterValue32((int)XtensaRegisters.PSOWB, value); 394 } 395 } 396 public RegistersGroup AR { get; private set; } 397 public RegistersGroup CONFIGID { get; private set; } 398 public RegistersGroup SCOMPARE { get; private set; } 399 public RegistersGroup IBREAKA { get; private set; } 400 public RegistersGroup DBREAKA { get; private set; } 401 public RegistersGroup DBREAKC { get; private set; } 402 public RegistersGroup EPC { get; private set; } 403 public RegistersGroup EPS { get; private set; } 404 public RegistersGroup EXCSAVE { get; private set; } 405 public RegistersGroup CCOMPARE { get; private set; } 406 public RegistersGroup MISC { get; private set; } 407 public RegistersGroup A { get; private set; } 408 InitializeRegisters()409 protected override void InitializeRegisters() 410 { 411 var indexValueMapAR = new Dictionary<int, XtensaRegisters> 412 { 413 { 0, XtensaRegisters.AR0 }, 414 { 1, XtensaRegisters.AR1 }, 415 { 2, XtensaRegisters.AR2 }, 416 { 3, XtensaRegisters.AR3 }, 417 { 4, XtensaRegisters.AR4 }, 418 { 5, XtensaRegisters.AR5 }, 419 { 6, XtensaRegisters.AR6 }, 420 { 7, XtensaRegisters.AR7 }, 421 { 8, XtensaRegisters.AR8 }, 422 { 9, XtensaRegisters.AR9 }, 423 { 10, XtensaRegisters.AR10 }, 424 { 11, XtensaRegisters.AR11 }, 425 { 12, XtensaRegisters.AR12 }, 426 { 13, XtensaRegisters.AR13 }, 427 { 14, XtensaRegisters.AR14 }, 428 { 15, XtensaRegisters.AR15 }, 429 { 16, XtensaRegisters.AR16 }, 430 { 17, XtensaRegisters.AR17 }, 431 { 18, XtensaRegisters.AR18 }, 432 { 19, XtensaRegisters.AR19 }, 433 { 20, XtensaRegisters.AR20 }, 434 { 21, XtensaRegisters.AR21 }, 435 { 22, XtensaRegisters.AR22 }, 436 { 23, XtensaRegisters.AR23 }, 437 { 24, XtensaRegisters.AR24 }, 438 { 25, XtensaRegisters.AR25 }, 439 { 26, XtensaRegisters.AR26 }, 440 { 27, XtensaRegisters.AR27 }, 441 { 28, XtensaRegisters.AR28 }, 442 { 29, XtensaRegisters.AR29 }, 443 { 30, XtensaRegisters.AR30 }, 444 { 31, XtensaRegisters.AR31 }, 445 }; 446 AR = new RegistersGroup( 447 indexValueMapAR.Keys, 448 i => GetRegister((int)indexValueMapAR[i]), 449 (i, v) => SetRegister((int)indexValueMapAR[i], v)); 450 451 var indexValueMapCONFIGID = new Dictionary<int, XtensaRegisters> 452 { 453 { 0, XtensaRegisters.CONFIGID0 }, 454 { 1, XtensaRegisters.CONFIGID1 }, 455 }; 456 CONFIGID = new RegistersGroup( 457 indexValueMapCONFIGID.Keys, 458 i => GetRegister((int)indexValueMapCONFIGID[i]), 459 (i, v) => SetRegister((int)indexValueMapCONFIGID[i], v)); 460 461 var indexValueMapSCOMPARE = new Dictionary<int, XtensaRegisters> 462 { 463 { 1, XtensaRegisters.SCOMPARE1 }, 464 }; 465 SCOMPARE = new RegistersGroup( 466 indexValueMapSCOMPARE.Keys, 467 i => GetRegister((int)indexValueMapSCOMPARE[i]), 468 (i, v) => SetRegister((int)indexValueMapSCOMPARE[i], v)); 469 470 var indexValueMapIBREAKA = new Dictionary<int, XtensaRegisters> 471 { 472 { 0, XtensaRegisters.IBREAKA0 }, 473 { 1, XtensaRegisters.IBREAKA1 }, 474 }; 475 IBREAKA = new RegistersGroup( 476 indexValueMapIBREAKA.Keys, 477 i => GetRegister((int)indexValueMapIBREAKA[i]), 478 (i, v) => SetRegister((int)indexValueMapIBREAKA[i], v)); 479 480 var indexValueMapDBREAKA = new Dictionary<int, XtensaRegisters> 481 { 482 { 0, XtensaRegisters.DBREAKA0 }, 483 { 1, XtensaRegisters.DBREAKA1 }, 484 }; 485 DBREAKA = new RegistersGroup( 486 indexValueMapDBREAKA.Keys, 487 i => GetRegister((int)indexValueMapDBREAKA[i]), 488 (i, v) => SetRegister((int)indexValueMapDBREAKA[i], v)); 489 490 var indexValueMapDBREAKC = new Dictionary<int, XtensaRegisters> 491 { 492 { 0, XtensaRegisters.DBREAKC0 }, 493 { 1, XtensaRegisters.DBREAKC1 }, 494 }; 495 DBREAKC = new RegistersGroup( 496 indexValueMapDBREAKC.Keys, 497 i => GetRegister((int)indexValueMapDBREAKC[i]), 498 (i, v) => SetRegister((int)indexValueMapDBREAKC[i], v)); 499 500 var indexValueMapEPC = new Dictionary<int, XtensaRegisters> 501 { 502 { 1, XtensaRegisters.EPC1 }, 503 { 2, XtensaRegisters.EPC2 }, 504 { 3, XtensaRegisters.EPC3 }, 505 { 4, XtensaRegisters.EPC4 }, 506 { 5, XtensaRegisters.EPC5 }, 507 { 6, XtensaRegisters.EPC6 }, 508 { 7, XtensaRegisters.EPC7 }, 509 }; 510 EPC = new RegistersGroup( 511 indexValueMapEPC.Keys, 512 i => GetRegister((int)indexValueMapEPC[i]), 513 (i, v) => SetRegister((int)indexValueMapEPC[i], v)); 514 515 var indexValueMapEPS = new Dictionary<int, XtensaRegisters> 516 { 517 { 2, XtensaRegisters.EPS2 }, 518 { 3, XtensaRegisters.EPS3 }, 519 { 4, XtensaRegisters.EPS4 }, 520 { 5, XtensaRegisters.EPS5 }, 521 { 6, XtensaRegisters.EPS6 }, 522 { 7, XtensaRegisters.EPS7 }, 523 }; 524 EPS = new RegistersGroup( 525 indexValueMapEPS.Keys, 526 i => GetRegister((int)indexValueMapEPS[i]), 527 (i, v) => SetRegister((int)indexValueMapEPS[i], v)); 528 529 var indexValueMapEXCSAVE = new Dictionary<int, XtensaRegisters> 530 { 531 { 1, XtensaRegisters.EXCSAVE1 }, 532 { 2, XtensaRegisters.EXCSAVE2 }, 533 { 3, XtensaRegisters.EXCSAVE3 }, 534 { 4, XtensaRegisters.EXCSAVE4 }, 535 { 5, XtensaRegisters.EXCSAVE5 }, 536 { 6, XtensaRegisters.EXCSAVE6 }, 537 { 7, XtensaRegisters.EXCSAVE7 }, 538 }; 539 EXCSAVE = new RegistersGroup( 540 indexValueMapEXCSAVE.Keys, 541 i => GetRegister((int)indexValueMapEXCSAVE[i]), 542 (i, v) => SetRegister((int)indexValueMapEXCSAVE[i], v)); 543 544 var indexValueMapCCOMPARE = new Dictionary<int, XtensaRegisters> 545 { 546 { 0, XtensaRegisters.CCOMPARE0 }, 547 { 1, XtensaRegisters.CCOMPARE1 }, 548 { 2, XtensaRegisters.CCOMPARE2 }, 549 }; 550 CCOMPARE = new RegistersGroup( 551 indexValueMapCCOMPARE.Keys, 552 i => GetRegister((int)indexValueMapCCOMPARE[i]), 553 (i, v) => SetRegister((int)indexValueMapCCOMPARE[i], v)); 554 555 var indexValueMapMISC = new Dictionary<int, XtensaRegisters> 556 { 557 { 0, XtensaRegisters.MISC0 }, 558 { 1, XtensaRegisters.MISC1 }, 559 }; 560 MISC = new RegistersGroup( 561 indexValueMapMISC.Keys, 562 i => GetRegister((int)indexValueMapMISC[i]), 563 (i, v) => SetRegister((int)indexValueMapMISC[i], v)); 564 565 var indexValueMapA = new Dictionary<int, XtensaRegisters> 566 { 567 { 0, XtensaRegisters.A0 }, 568 { 1, XtensaRegisters.A1 }, 569 { 2, XtensaRegisters.A2 }, 570 { 3, XtensaRegisters.A3 }, 571 { 4, XtensaRegisters.A4 }, 572 { 5, XtensaRegisters.A5 }, 573 { 6, XtensaRegisters.A6 }, 574 { 7, XtensaRegisters.A7 }, 575 { 8, XtensaRegisters.A8 }, 576 { 9, XtensaRegisters.A9 }, 577 { 10, XtensaRegisters.A10 }, 578 { 11, XtensaRegisters.A11 }, 579 { 12, XtensaRegisters.A12 }, 580 { 13, XtensaRegisters.A13 }, 581 { 14, XtensaRegisters.A14 }, 582 { 15, XtensaRegisters.A15 }, 583 }; 584 A = new RegistersGroup( 585 indexValueMapA.Keys, 586 i => GetRegister((int)indexValueMapA[i]), 587 (i, v) => SetRegister((int)indexValueMapA[i], v)); 588 589 } 590 591 // 649: Field '...' is never assigned to, and will always have its default value null 592 #pragma warning disable 649 593 594 [Import(Name = "tlib_set_register_value_32")] 595 protected Action<int, uint> SetRegisterValue32; 596 [Import(Name = "tlib_get_register_value_32")] 597 protected Func<int, uint> GetRegisterValue32; 598 599 #pragma warning restore 649 600 601 private static readonly Dictionary<XtensaRegisters, CPURegister> mapping = new Dictionary<XtensaRegisters, CPURegister> 602 { 603 { XtensaRegisters.PC, new CPURegister(0, 32, isGeneral: true, isReadonly: false, aliases: new [] { "PC" }) }, 604 { XtensaRegisters.AR0, new CPURegister(1, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR0" }) }, 605 { XtensaRegisters.AR1, new CPURegister(2, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR1" }) }, 606 { XtensaRegisters.AR2, new CPURegister(3, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR2" }) }, 607 { XtensaRegisters.AR3, new CPURegister(4, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR3" }) }, 608 { XtensaRegisters.AR4, new CPURegister(5, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR4" }) }, 609 { XtensaRegisters.AR5, new CPURegister(6, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR5" }) }, 610 { XtensaRegisters.AR6, new CPURegister(7, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR6" }) }, 611 { XtensaRegisters.AR7, new CPURegister(8, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR7" }) }, 612 { XtensaRegisters.AR8, new CPURegister(9, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR8" }) }, 613 { XtensaRegisters.AR9, new CPURegister(10, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR9" }) }, 614 { XtensaRegisters.AR10, new CPURegister(11, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR10" }) }, 615 { XtensaRegisters.AR11, new CPURegister(12, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR11" }) }, 616 { XtensaRegisters.AR12, new CPURegister(13, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR12" }) }, 617 { XtensaRegisters.AR13, new CPURegister(14, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR13" }) }, 618 { XtensaRegisters.AR14, new CPURegister(15, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR14" }) }, 619 { XtensaRegisters.AR15, new CPURegister(16, 32, isGeneral: true, isReadonly: false, aliases: new [] { "AR15" }) }, 620 { XtensaRegisters.AR16, new CPURegister(17, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR16" }) }, 621 { XtensaRegisters.AR17, new CPURegister(18, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR17" }) }, 622 { XtensaRegisters.AR18, new CPURegister(19, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR18" }) }, 623 { XtensaRegisters.AR19, new CPURegister(20, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR19" }) }, 624 { XtensaRegisters.AR20, new CPURegister(21, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR20" }) }, 625 { XtensaRegisters.AR21, new CPURegister(22, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR21" }) }, 626 { XtensaRegisters.AR22, new CPURegister(23, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR22" }) }, 627 { XtensaRegisters.AR23, new CPURegister(24, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR23" }) }, 628 { XtensaRegisters.AR24, new CPURegister(25, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR24" }) }, 629 { XtensaRegisters.AR25, new CPURegister(26, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR25" }) }, 630 { XtensaRegisters.AR26, new CPURegister(27, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR26" }) }, 631 { XtensaRegisters.AR27, new CPURegister(28, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR27" }) }, 632 { XtensaRegisters.AR28, new CPURegister(29, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR28" }) }, 633 { XtensaRegisters.AR29, new CPURegister(30, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR29" }) }, 634 { XtensaRegisters.AR30, new CPURegister(31, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR30" }) }, 635 { XtensaRegisters.AR31, new CPURegister(32, 32, isGeneral: false, isReadonly: false, aliases: new [] { "AR31" }) }, 636 { XtensaRegisters.SAR, new CPURegister(33, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SAR" }) }, 637 { XtensaRegisters.WINDOWBASE, new CPURegister(34, 32, isGeneral: false, isReadonly: false, aliases: new [] { "WINDOWBASE" }) }, 638 { XtensaRegisters.WINDOWSTART, new CPURegister(35, 32, isGeneral: false, isReadonly: false, aliases: new [] { "WINDOWSTART" }) }, 639 { XtensaRegisters.CONFIGID0, new CPURegister(36, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CONFIGID0" }) }, 640 { XtensaRegisters.CONFIGID1, new CPURegister(37, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CONFIGID1" }) }, 641 { XtensaRegisters.PS, new CPURegister(38, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PS" }) }, 642 { XtensaRegisters.SCOMPARE1, new CPURegister(39, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SCOMPARE1" }) }, 643 { XtensaRegisters.EXPSTATE, new CPURegister(40, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXPSTATE" }) }, 644 { XtensaRegisters.MMID, new CPURegister(41, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MMID" }) }, 645 { XtensaRegisters.IBREAKENABLE, new CPURegister(42, 32, isGeneral: false, isReadonly: false, aliases: new [] { "IBREAKENABLE" }) }, 646 { XtensaRegisters.ATOMCTL, new CPURegister(43, 32, isGeneral: false, isReadonly: false, aliases: new [] { "ATOMCTL" }) }, 647 { XtensaRegisters.DDR, new CPURegister(44, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DDR" }) }, 648 { XtensaRegisters.IBREAKA0, new CPURegister(45, 32, isGeneral: false, isReadonly: false, aliases: new [] { "IBREAKA0" }) }, 649 { XtensaRegisters.IBREAKA1, new CPURegister(46, 32, isGeneral: false, isReadonly: false, aliases: new [] { "IBREAKA1" }) }, 650 { XtensaRegisters.DBREAKA0, new CPURegister(47, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DBREAKA0" }) }, 651 { XtensaRegisters.DBREAKA1, new CPURegister(48, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DBREAKA1" }) }, 652 { XtensaRegisters.DBREAKC0, new CPURegister(49, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DBREAKC0" }) }, 653 { XtensaRegisters.DBREAKC1, new CPURegister(50, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DBREAKC1" }) }, 654 { XtensaRegisters.EPC1, new CPURegister(51, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC1" }) }, 655 { XtensaRegisters.EPC2, new CPURegister(52, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC2" }) }, 656 { XtensaRegisters.EPC3, new CPURegister(53, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC3" }) }, 657 { XtensaRegisters.EPC4, new CPURegister(54, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC4" }) }, 658 { XtensaRegisters.EPC5, new CPURegister(55, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC5" }) }, 659 { XtensaRegisters.EPC6, new CPURegister(56, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC6" }) }, 660 { XtensaRegisters.EPC7, new CPURegister(57, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPC7" }) }, 661 { XtensaRegisters.DEPC, new CPURegister(58, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DEPC" }) }, 662 { XtensaRegisters.EPS2, new CPURegister(59, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS2" }) }, 663 { XtensaRegisters.EPS3, new CPURegister(60, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS3" }) }, 664 { XtensaRegisters.EPS4, new CPURegister(61, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS4" }) }, 665 { XtensaRegisters.EPS5, new CPURegister(62, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS5" }) }, 666 { XtensaRegisters.EPS6, new CPURegister(63, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS6" }) }, 667 { XtensaRegisters.EPS7, new CPURegister(64, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EPS7" }) }, 668 { XtensaRegisters.EXCSAVE1, new CPURegister(65, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE1" }) }, 669 { XtensaRegisters.EXCSAVE2, new CPURegister(66, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE2" }) }, 670 { XtensaRegisters.EXCSAVE3, new CPURegister(67, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE3" }) }, 671 { XtensaRegisters.EXCSAVE4, new CPURegister(68, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE4" }) }, 672 { XtensaRegisters.EXCSAVE5, new CPURegister(69, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE5" }) }, 673 { XtensaRegisters.EXCSAVE6, new CPURegister(70, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE6" }) }, 674 { XtensaRegisters.EXCSAVE7, new CPURegister(71, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCSAVE7" }) }, 675 { XtensaRegisters.INTERRUPT, new CPURegister(72, 32, isGeneral: false, isReadonly: true, aliases: new [] { "INTERRUPT" }) }, 676 { XtensaRegisters.INTSET, new CPURegister(73, 32, isGeneral: false, isReadonly: false, aliases: new [] { "INTSET" }) }, 677 { XtensaRegisters.INTCLEAR, new CPURegister(74, 32, isGeneral: false, isReadonly: false, aliases: new [] { "INTCLEAR" }) }, 678 { XtensaRegisters.INTENABLE, new CPURegister(75, 32, isGeneral: false, isReadonly: false, aliases: new [] { "INTENABLE" }) }, 679 { XtensaRegisters.VECBASE, new CPURegister(76, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VECBASE" }) }, 680 { XtensaRegisters.EXCCAUSE, new CPURegister(77, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCCAUSE" }) }, 681 { XtensaRegisters.DEBUGCAUSE, new CPURegister(78, 32, isGeneral: false, isReadonly: false, aliases: new [] { "DEBUGCAUSE" }) }, 682 { XtensaRegisters.CCOUNT, new CPURegister(79, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CCOUNT" }) }, 683 { XtensaRegisters.PRID, new CPURegister(80, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PRID" }) }, 684 { XtensaRegisters.ICOUNT, new CPURegister(81, 32, isGeneral: false, isReadonly: false, aliases: new [] { "ICOUNT" }) }, 685 { XtensaRegisters.ICOUNTLEVEL, new CPURegister(82, 32, isGeneral: false, isReadonly: false, aliases: new [] { "ICOUNTLEVEL" }) }, 686 { XtensaRegisters.EXCVADDR, new CPURegister(83, 32, isGeneral: false, isReadonly: false, aliases: new [] { "EXCVADDR" }) }, 687 { XtensaRegisters.CCOMPARE0, new CPURegister(84, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CCOMPARE0" }) }, 688 { XtensaRegisters.CCOMPARE1, new CPURegister(85, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CCOMPARE1" }) }, 689 { XtensaRegisters.CCOMPARE2, new CPURegister(86, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CCOMPARE2" }) }, 690 { XtensaRegisters.MISC0, new CPURegister(87, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MISC0" }) }, 691 { XtensaRegisters.MISC1, new CPURegister(88, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MISC1" }) }, 692 { XtensaRegisters.A0, new CPURegister(89, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A0" }) }, 693 { XtensaRegisters.A1, new CPURegister(90, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A1" }) }, 694 { XtensaRegisters.A2, new CPURegister(91, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A2" }) }, 695 { XtensaRegisters.A3, new CPURegister(92, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A3" }) }, 696 { XtensaRegisters.A4, new CPURegister(93, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A4" }) }, 697 { XtensaRegisters.A5, new CPURegister(94, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A5" }) }, 698 { XtensaRegisters.A6, new CPURegister(95, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A6" }) }, 699 { XtensaRegisters.A7, new CPURegister(96, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A7" }) }, 700 { XtensaRegisters.A8, new CPURegister(97, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A8" }) }, 701 { XtensaRegisters.A9, new CPURegister(98, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A9" }) }, 702 { XtensaRegisters.A10, new CPURegister(99, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A10" }) }, 703 { XtensaRegisters.A11, new CPURegister(100, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A11" }) }, 704 { XtensaRegisters.A12, new CPURegister(101, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A12" }) }, 705 { XtensaRegisters.A13, new CPURegister(102, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A13" }) }, 706 { XtensaRegisters.A14, new CPURegister(103, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A14" }) }, 707 { XtensaRegisters.A15, new CPURegister(104, 32, isGeneral: false, isReadonly: false, aliases: new [] { "A15" }) }, 708 { XtensaRegisters.PSINTLEVEL, new CPURegister(105, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSINTLEVEL" }) }, 709 { XtensaRegisters.PSUM, new CPURegister(106, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSUM" }) }, 710 { XtensaRegisters.PSWOE, new CPURegister(107, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSWOE" }) }, 711 { XtensaRegisters.PSEXCM, new CPURegister(108, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSEXCM" }) }, 712 { XtensaRegisters.PSCALLINC, new CPURegister(109, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSCALLINC" }) }, 713 { XtensaRegisters.PSOWB, new CPURegister(110, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PSOWB" }) }, 714 }; 715 } 716 717 public enum XtensaRegisters 718 { 719 PC = 0, 720 SAR = 33, 721 WINDOWBASE = 34, 722 WINDOWSTART = 35, 723 PS = 38, 724 EXPSTATE = 40, 725 MMID = 41, 726 IBREAKENABLE = 42, 727 ATOMCTL = 43, 728 DDR = 44, 729 DEPC = 58, 730 INTERRUPT = 72, 731 INTSET = 73, 732 INTCLEAR = 74, 733 INTENABLE = 75, 734 VECBASE = 76, 735 EXCCAUSE = 77, 736 DEBUGCAUSE = 78, 737 CCOUNT = 79, 738 PRID = 80, 739 ICOUNT = 81, 740 ICOUNTLEVEL = 82, 741 EXCVADDR = 83, 742 PSINTLEVEL = 105, 743 PSUM = 106, 744 PSWOE = 107, 745 PSEXCM = 108, 746 PSCALLINC = 109, 747 PSOWB = 110, 748 AR0 = 1, 749 AR1 = 2, 750 AR2 = 3, 751 AR3 = 4, 752 AR4 = 5, 753 AR5 = 6, 754 AR6 = 7, 755 AR7 = 8, 756 AR8 = 9, 757 AR9 = 10, 758 AR10 = 11, 759 AR11 = 12, 760 AR12 = 13, 761 AR13 = 14, 762 AR14 = 15, 763 AR15 = 16, 764 AR16 = 17, 765 AR17 = 18, 766 AR18 = 19, 767 AR19 = 20, 768 AR20 = 21, 769 AR21 = 22, 770 AR22 = 23, 771 AR23 = 24, 772 AR24 = 25, 773 AR25 = 26, 774 AR26 = 27, 775 AR27 = 28, 776 AR28 = 29, 777 AR29 = 30, 778 AR30 = 31, 779 AR31 = 32, 780 CONFIGID0 = 36, 781 CONFIGID1 = 37, 782 SCOMPARE1 = 39, 783 IBREAKA0 = 45, 784 IBREAKA1 = 46, 785 DBREAKA0 = 47, 786 DBREAKA1 = 48, 787 DBREAKC0 = 49, 788 DBREAKC1 = 50, 789 EPC1 = 51, 790 EPC2 = 52, 791 EPC3 = 53, 792 EPC4 = 54, 793 EPC5 = 55, 794 EPC6 = 56, 795 EPC7 = 57, 796 EPS2 = 59, 797 EPS3 = 60, 798 EPS4 = 61, 799 EPS5 = 62, 800 EPS6 = 63, 801 EPS7 = 64, 802 EXCSAVE1 = 65, 803 EXCSAVE2 = 66, 804 EXCSAVE3 = 67, 805 EXCSAVE4 = 68, 806 EXCSAVE5 = 69, 807 EXCSAVE6 = 70, 808 EXCSAVE7 = 71, 809 CCOMPARE0 = 84, 810 CCOMPARE1 = 85, 811 CCOMPARE2 = 86, 812 MISC0 = 87, 813 MISC1 = 88, 814 A0 = 89, 815 A1 = 90, 816 A2 = 91, 817 A3 = 92, 818 A4 = 93, 819 A5 = 94, 820 A6 = 95, 821 A7 = 96, 822 A8 = 97, 823 A9 = 98, 824 A10 = 99, 825 A11 = 100, 826 A12 = 101, 827 A13 = 102, 828 A14 = 103, 829 A15 = 104, 830 } 831 } 832
