1 /******************************************************** 2 * 3 * Warning! 4 * This file was generated automatically. 5 * Please do not edit. Changes should be made in the 6 * appropriate *.tt file. 7 * 8 */ 9 using System; 10 using System.Linq; 11 using System.Collections.Generic; 12 using Antmicro.Renode.Peripherals.CPU.Registers; 13 using Antmicro.Renode.Utilities.Binding; 14 using Antmicro.Renode.Exceptions; 15 16 namespace Antmicro.Renode.Peripherals.CPU 17 { 18 public partial class RiscV64 19 { SetRegister(int register, RegisterValue value)20 public override void SetRegister(int register, RegisterValue value) 21 { 22 if(!mapping.TryGetValue((RiscV64Registers)register, out var r)) 23 { 24 if(TrySetNonMappedRegister(register, value)) 25 { 26 return; 27 } 28 throw new RecoverableException($"Wrong register index: {register}"); 29 } 30 if(r.IsReadonly) 31 { 32 throw new RecoverableException($"The '{(RiscV64Registers)register}' register is read-only."); 33 } 34 35 SetRegisterValue64(r.Index, checked((ulong)value)); 36 } 37 GetRegister(int register)38 public override RegisterValue GetRegister(int register) 39 { 40 if(!mapping.TryGetValue((RiscV64Registers)register, out var r)) 41 { 42 if(TryGetNonMappedRegister(register, out var value)) 43 { 44 return value; 45 } 46 throw new RecoverableException($"Wrong register index: {register}"); 47 } 48 return GetRegisterValue64(r.Index); 49 } 50 GetRegisters()51 public override IEnumerable<CPURegister> GetRegisters() 52 { 53 return mapping.Values.Concat(GetNonMappedRegisters()).OrderBy(x => x.Index); 54 } 55 56 [Register] 57 public RegisterValue ZERO 58 { 59 get 60 { 61 return GetRegisterValue64((int)RiscV64Registers.ZERO); 62 } 63 set 64 { 65 SetRegisterValue64((int)RiscV64Registers.ZERO, value); 66 } 67 } 68 [Register] 69 public RegisterValue RA 70 { 71 get 72 { 73 return GetRegisterValue64((int)RiscV64Registers.RA); 74 } 75 set 76 { 77 SetRegisterValue64((int)RiscV64Registers.RA, value); 78 } 79 } 80 [Register] 81 public RegisterValue SP 82 { 83 get 84 { 85 return GetRegisterValue64((int)RiscV64Registers.SP); 86 } 87 set 88 { 89 SetRegisterValue64((int)RiscV64Registers.SP, value); 90 } 91 } 92 [Register] 93 public RegisterValue GP 94 { 95 get 96 { 97 return GetRegisterValue64((int)RiscV64Registers.GP); 98 } 99 set 100 { 101 SetRegisterValue64((int)RiscV64Registers.GP, value); 102 } 103 } 104 [Register] 105 public RegisterValue TP 106 { 107 get 108 { 109 return GetRegisterValue64((int)RiscV64Registers.TP); 110 } 111 set 112 { 113 SetRegisterValue64((int)RiscV64Registers.TP, value); 114 } 115 } 116 [Register] 117 public RegisterValue FP 118 { 119 get 120 { 121 return GetRegisterValue64((int)RiscV64Registers.FP); 122 } 123 set 124 { 125 SetRegisterValue64((int)RiscV64Registers.FP, value); 126 } 127 } 128 [Register] 129 public override RegisterValue PC 130 { 131 get 132 { 133 return GetRegisterValue64((int)RiscV64Registers.PC); 134 } 135 set 136 { 137 value = BeforePCWrite(value); 138 SetRegisterValue64((int)RiscV64Registers.PC, value); 139 } 140 } 141 [Register] 142 public RegisterValue SSTATUS 143 { 144 get 145 { 146 return GetRegisterValue64((int)RiscV64Registers.SSTATUS); 147 } 148 set 149 { 150 SetRegisterValue64((int)RiscV64Registers.SSTATUS, value); 151 } 152 } 153 [Register] 154 public RegisterValue SIE 155 { 156 get 157 { 158 return GetRegisterValue64((int)RiscV64Registers.SIE); 159 } 160 set 161 { 162 SetRegisterValue64((int)RiscV64Registers.SIE, value); 163 } 164 } 165 [Register] 166 public RegisterValue STVEC 167 { 168 get 169 { 170 return GetRegisterValue64((int)RiscV64Registers.STVEC); 171 } 172 set 173 { 174 value = BeforeSTVECWrite(value); 175 SetRegisterValue64((int)RiscV64Registers.STVEC, value); 176 } 177 } 178 [Register] 179 public RegisterValue SSCRATCH 180 { 181 get 182 { 183 return GetRegisterValue64((int)RiscV64Registers.SSCRATCH); 184 } 185 set 186 { 187 SetRegisterValue64((int)RiscV64Registers.SSCRATCH, value); 188 } 189 } 190 [Register] 191 public RegisterValue SEPC 192 { 193 get 194 { 195 return GetRegisterValue64((int)RiscV64Registers.SEPC); 196 } 197 set 198 { 199 SetRegisterValue64((int)RiscV64Registers.SEPC, value); 200 } 201 } 202 [Register] 203 public RegisterValue SCAUSE 204 { 205 get 206 { 207 return GetRegisterValue64((int)RiscV64Registers.SCAUSE); 208 } 209 set 210 { 211 SetRegisterValue64((int)RiscV64Registers.SCAUSE, value); 212 } 213 } 214 [Register] 215 public RegisterValue STVAL 216 { 217 get 218 { 219 return GetRegisterValue64((int)RiscV64Registers.STVAL); 220 } 221 set 222 { 223 SetRegisterValue64((int)RiscV64Registers.STVAL, value); 224 } 225 } 226 [Register] 227 public RegisterValue SIP 228 { 229 get 230 { 231 return GetRegisterValue64((int)RiscV64Registers.SIP); 232 } 233 set 234 { 235 SetRegisterValue64((int)RiscV64Registers.SIP, value); 236 } 237 } 238 [Register] 239 public RegisterValue SATP 240 { 241 get 242 { 243 return GetRegisterValue64((int)RiscV64Registers.SATP); 244 } 245 set 246 { 247 SetRegisterValue64((int)RiscV64Registers.SATP, value); 248 } 249 } 250 [Register] 251 public RegisterValue SPTBR 252 { 253 get 254 { 255 return GetRegisterValue64((int)RiscV64Registers.SPTBR); 256 } 257 set 258 { 259 SetRegisterValue64((int)RiscV64Registers.SPTBR, value); 260 } 261 } 262 [Register] 263 public RegisterValue MSTATUS 264 { 265 get 266 { 267 return GetRegisterValue64((int)RiscV64Registers.MSTATUS); 268 } 269 set 270 { 271 SetRegisterValue64((int)RiscV64Registers.MSTATUS, value); 272 } 273 } 274 [Register] 275 public RegisterValue MISA 276 { 277 get 278 { 279 return GetRegisterValue64((int)RiscV64Registers.MISA); 280 } 281 set 282 { 283 SetRegisterValue64((int)RiscV64Registers.MISA, value); 284 } 285 } 286 [Register] 287 public RegisterValue MEDELEG 288 { 289 get 290 { 291 return GetRegisterValue64((int)RiscV64Registers.MEDELEG); 292 } 293 set 294 { 295 SetRegisterValue64((int)RiscV64Registers.MEDELEG, value); 296 } 297 } 298 [Register] 299 public RegisterValue MIDELEG 300 { 301 get 302 { 303 return GetRegisterValue64((int)RiscV64Registers.MIDELEG); 304 } 305 set 306 { 307 SetRegisterValue64((int)RiscV64Registers.MIDELEG, value); 308 } 309 } 310 [Register] 311 public RegisterValue MIE 312 { 313 get 314 { 315 return GetRegisterValue64((int)RiscV64Registers.MIE); 316 } 317 set 318 { 319 SetRegisterValue64((int)RiscV64Registers.MIE, value); 320 } 321 } 322 [Register] 323 public RegisterValue MTVEC 324 { 325 get 326 { 327 return GetRegisterValue64((int)RiscV64Registers.MTVEC); 328 } 329 set 330 { 331 value = BeforeMTVECWrite(value); 332 SetRegisterValue64((int)RiscV64Registers.MTVEC, value); 333 } 334 } 335 [Register] 336 public RegisterValue MSCRATCH 337 { 338 get 339 { 340 return GetRegisterValue64((int)RiscV64Registers.MSCRATCH); 341 } 342 set 343 { 344 SetRegisterValue64((int)RiscV64Registers.MSCRATCH, value); 345 } 346 } 347 [Register] 348 public RegisterValue MEPC 349 { 350 get 351 { 352 return GetRegisterValue64((int)RiscV64Registers.MEPC); 353 } 354 set 355 { 356 SetRegisterValue64((int)RiscV64Registers.MEPC, value); 357 } 358 } 359 [Register] 360 public RegisterValue MCAUSE 361 { 362 get 363 { 364 return GetRegisterValue64((int)RiscV64Registers.MCAUSE); 365 } 366 set 367 { 368 SetRegisterValue64((int)RiscV64Registers.MCAUSE, value); 369 } 370 } 371 [Register] 372 public RegisterValue MTVAL 373 { 374 get 375 { 376 return GetRegisterValue64((int)RiscV64Registers.MTVAL); 377 } 378 set 379 { 380 SetRegisterValue64((int)RiscV64Registers.MTVAL, value); 381 } 382 } 383 [Register] 384 public RegisterValue MIP 385 { 386 get 387 { 388 return GetRegisterValue64((int)RiscV64Registers.MIP); 389 } 390 set 391 { 392 SetRegisterValue64((int)RiscV64Registers.MIP, value); 393 } 394 } 395 [Register] 396 public RegisterValue PRIV 397 { 398 get 399 { 400 return GetRegisterValue64((int)RiscV64Registers.PRIV); 401 } 402 set 403 { 404 SetRegisterValue64((int)RiscV64Registers.PRIV, value); 405 } 406 } 407 [Register] 408 public RegisterValue VSTART 409 { 410 get 411 { 412 BeforeVectorExtensionRegisterRead(); 413 return GetRegisterValue64((int)RiscV64Registers.VSTART); 414 } 415 set 416 { 417 value = BeforeVectorExtensionRegisterWrite(value); 418 SetRegisterValue64((int)RiscV64Registers.VSTART, value); 419 } 420 } 421 [Register] 422 public RegisterValue VXSAT 423 { 424 get 425 { 426 BeforeVectorExtensionRegisterRead(); 427 return GetRegisterValue64((int)RiscV64Registers.VXSAT); 428 } 429 set 430 { 431 value = BeforeVectorExtensionRegisterWrite(value); 432 SetRegisterValue64((int)RiscV64Registers.VXSAT, value); 433 } 434 } 435 [Register] 436 public RegisterValue VXRM 437 { 438 get 439 { 440 BeforeVectorExtensionRegisterRead(); 441 return GetRegisterValue64((int)RiscV64Registers.VXRM); 442 } 443 set 444 { 445 value = BeforeVectorExtensionRegisterWrite(value); 446 SetRegisterValue64((int)RiscV64Registers.VXRM, value); 447 } 448 } 449 [Register] 450 public RegisterValue VCSR 451 { 452 get 453 { 454 BeforeVectorExtensionRegisterRead(); 455 return GetRegisterValue64((int)RiscV64Registers.VCSR); 456 } 457 set 458 { 459 value = BeforeVectorExtensionRegisterWrite(value); 460 SetRegisterValue64((int)RiscV64Registers.VCSR, value); 461 } 462 } 463 [Register] 464 public RegisterValue MSECCFG 465 { 466 get 467 { 468 return GetRegisterValue64((int)RiscV64Registers.MSECCFG); 469 } 470 set 471 { 472 SetRegisterValue64((int)RiscV64Registers.MSECCFG, value); 473 } 474 } 475 [Register] 476 public RegisterValue VL 477 { 478 get 479 { 480 BeforeVectorExtensionRegisterRead(); 481 return GetRegisterValue64((int)RiscV64Registers.VL); 482 } 483 set 484 { 485 value = BeforeVectorExtensionRegisterWrite(value); 486 SetRegisterValue64((int)RiscV64Registers.VL, value); 487 } 488 } 489 [Register] 490 public RegisterValue VTYPE 491 { 492 get 493 { 494 BeforeVectorExtensionRegisterRead(); 495 return GetRegisterValue64((int)RiscV64Registers.VTYPE); 496 } 497 set 498 { 499 value = BeforeVectorExtensionRegisterWrite(value); 500 SetRegisterValue64((int)RiscV64Registers.VTYPE, value); 501 } 502 } 503 [Register] 504 public RegisterValue VLENB 505 { 506 get 507 { 508 BeforeVectorExtensionRegisterRead(); 509 return GetRegisterValue64((int)RiscV64Registers.VLENB); 510 } 511 set 512 { 513 value = BeforeVectorExtensionRegisterWrite(value); 514 SetRegisterValue64((int)RiscV64Registers.VLENB, value); 515 } 516 } 517 public RegistersGroup X { get; private set; } 518 public RegistersGroup T { get; private set; } 519 public RegistersGroup S { get; private set; } 520 public RegistersGroup A { get; private set; } 521 public RegistersGroup F { get; private set; } 522 InitializeRegisters()523 protected override void InitializeRegisters() 524 { 525 var indexValueMapX = new Dictionary<int, RiscV64Registers> 526 { 527 { 0, RiscV64Registers.X0 }, 528 { 1, RiscV64Registers.X1 }, 529 { 2, RiscV64Registers.X2 }, 530 { 3, RiscV64Registers.X3 }, 531 { 4, RiscV64Registers.X4 }, 532 { 5, RiscV64Registers.X5 }, 533 { 6, RiscV64Registers.X6 }, 534 { 7, RiscV64Registers.X7 }, 535 { 8, RiscV64Registers.X8 }, 536 { 9, RiscV64Registers.X9 }, 537 { 10, RiscV64Registers.X10 }, 538 { 11, RiscV64Registers.X11 }, 539 { 12, RiscV64Registers.X12 }, 540 { 13, RiscV64Registers.X13 }, 541 { 14, RiscV64Registers.X14 }, 542 { 15, RiscV64Registers.X15 }, 543 { 16, RiscV64Registers.X16 }, 544 { 17, RiscV64Registers.X17 }, 545 { 18, RiscV64Registers.X18 }, 546 { 19, RiscV64Registers.X19 }, 547 { 20, RiscV64Registers.X20 }, 548 { 21, RiscV64Registers.X21 }, 549 { 22, RiscV64Registers.X22 }, 550 { 23, RiscV64Registers.X23 }, 551 { 24, RiscV64Registers.X24 }, 552 { 25, RiscV64Registers.X25 }, 553 { 26, RiscV64Registers.X26 }, 554 { 27, RiscV64Registers.X27 }, 555 { 28, RiscV64Registers.X28 }, 556 { 29, RiscV64Registers.X29 }, 557 { 30, RiscV64Registers.X30 }, 558 { 31, RiscV64Registers.X31 }, 559 }; 560 X = new RegistersGroup( 561 indexValueMapX.Keys, 562 i => GetRegister((int)indexValueMapX[i]), 563 (i, v) => SetRegister((int)indexValueMapX[i], v)); 564 565 var indexValueMapT = new Dictionary<int, RiscV64Registers> 566 { 567 { 0, RiscV64Registers.T0 }, 568 { 1, RiscV64Registers.T1 }, 569 { 2, RiscV64Registers.T2 }, 570 { 3, RiscV64Registers.T3 }, 571 { 4, RiscV64Registers.T4 }, 572 { 5, RiscV64Registers.T5 }, 573 { 6, RiscV64Registers.T6 }, 574 }; 575 T = new RegistersGroup( 576 indexValueMapT.Keys, 577 i => GetRegister((int)indexValueMapT[i]), 578 (i, v) => SetRegister((int)indexValueMapT[i], v)); 579 580 var indexValueMapS = new Dictionary<int, RiscV64Registers> 581 { 582 { 0, RiscV64Registers.S0 }, 583 { 1, RiscV64Registers.S1 }, 584 { 2, RiscV64Registers.S2 }, 585 { 3, RiscV64Registers.S3 }, 586 { 4, RiscV64Registers.S4 }, 587 { 5, RiscV64Registers.S5 }, 588 { 6, RiscV64Registers.S6 }, 589 { 7, RiscV64Registers.S7 }, 590 { 8, RiscV64Registers.S8 }, 591 { 9, RiscV64Registers.S9 }, 592 { 10, RiscV64Registers.S10 }, 593 { 11, RiscV64Registers.S11 }, 594 }; 595 S = new RegistersGroup( 596 indexValueMapS.Keys, 597 i => GetRegister((int)indexValueMapS[i]), 598 (i, v) => SetRegister((int)indexValueMapS[i], v)); 599 600 var indexValueMapA = new Dictionary<int, RiscV64Registers> 601 { 602 { 0, RiscV64Registers.A0 }, 603 { 1, RiscV64Registers.A1 }, 604 { 2, RiscV64Registers.A2 }, 605 { 3, RiscV64Registers.A3 }, 606 { 4, RiscV64Registers.A4 }, 607 { 5, RiscV64Registers.A5 }, 608 { 6, RiscV64Registers.A6 }, 609 { 7, RiscV64Registers.A7 }, 610 }; 611 A = new RegistersGroup( 612 indexValueMapA.Keys, 613 i => GetRegister((int)indexValueMapA[i]), 614 (i, v) => SetRegister((int)indexValueMapA[i], v)); 615 616 var indexValueMapF = new Dictionary<int, RiscV64Registers> 617 { 618 { 0, RiscV64Registers.F0 }, 619 { 1, RiscV64Registers.F1 }, 620 { 2, RiscV64Registers.F2 }, 621 { 3, RiscV64Registers.F3 }, 622 { 4, RiscV64Registers.F4 }, 623 { 5, RiscV64Registers.F5 }, 624 { 6, RiscV64Registers.F6 }, 625 { 7, RiscV64Registers.F7 }, 626 { 8, RiscV64Registers.F8 }, 627 { 9, RiscV64Registers.F9 }, 628 { 10, RiscV64Registers.F10 }, 629 { 11, RiscV64Registers.F11 }, 630 { 12, RiscV64Registers.F12 }, 631 { 13, RiscV64Registers.F13 }, 632 { 14, RiscV64Registers.F14 }, 633 { 15, RiscV64Registers.F15 }, 634 { 16, RiscV64Registers.F16 }, 635 { 17, RiscV64Registers.F17 }, 636 { 18, RiscV64Registers.F18 }, 637 { 19, RiscV64Registers.F19 }, 638 { 20, RiscV64Registers.F20 }, 639 { 21, RiscV64Registers.F21 }, 640 { 22, RiscV64Registers.F22 }, 641 { 23, RiscV64Registers.F23 }, 642 { 24, RiscV64Registers.F24 }, 643 { 25, RiscV64Registers.F25 }, 644 { 26, RiscV64Registers.F26 }, 645 { 27, RiscV64Registers.F27 }, 646 { 28, RiscV64Registers.F28 }, 647 { 29, RiscV64Registers.F29 }, 648 { 30, RiscV64Registers.F30 }, 649 { 31, RiscV64Registers.F31 }, 650 }; 651 F = new RegistersGroup( 652 indexValueMapF.Keys, 653 i => GetRegister((int)indexValueMapF[i]), 654 (i, v) => SetRegister((int)indexValueMapF[i], v)); 655 656 } 657 658 // 649: Field '...' is never assigned to, and will always have its default value null 659 #pragma warning disable 649 660 661 [Import(Name = "tlib_set_register_value_64")] 662 protected Action<int, ulong> SetRegisterValue64; 663 [Import(Name = "tlib_get_register_value_64")] 664 protected Func<int, ulong> GetRegisterValue64; 665 666 #pragma warning restore 649 667 668 private static readonly Dictionary<RiscV64Registers, CPURegister> mapping = new Dictionary<RiscV64Registers, CPURegister> 669 { 670 { RiscV64Registers.ZERO, new CPURegister(0, 64, isGeneral: true, isReadonly: true, aliases: new [] { "ZERO", "X0" }) }, 671 { RiscV64Registers.RA, new CPURegister(1, 64, isGeneral: true, isReadonly: false, aliases: new [] { "RA", "X1" }) }, 672 { RiscV64Registers.SP, new CPURegister(2, 64, isGeneral: true, isReadonly: false, aliases: new [] { "SP", "X2" }) }, 673 { RiscV64Registers.GP, new CPURegister(3, 64, isGeneral: true, isReadonly: false, aliases: new [] { "GP", "X3" }) }, 674 { RiscV64Registers.TP, new CPURegister(4, 64, isGeneral: true, isReadonly: false, aliases: new [] { "TP", "X4" }) }, 675 { RiscV64Registers.X5, new CPURegister(5, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X5", "T0" }) }, 676 { RiscV64Registers.X6, new CPURegister(6, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X6", "T1" }) }, 677 { RiscV64Registers.X7, new CPURegister(7, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X7", "T2" }) }, 678 { RiscV64Registers.FP, new CPURegister(8, 64, isGeneral: true, isReadonly: false, aliases: new [] { "FP", "X8", "S0" }) }, 679 { RiscV64Registers.X9, new CPURegister(9, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X9", "S1" }) }, 680 { RiscV64Registers.X10, new CPURegister(10, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X10", "A0" }) }, 681 { RiscV64Registers.X11, new CPURegister(11, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X11", "A1" }) }, 682 { RiscV64Registers.X12, new CPURegister(12, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X12", "A2" }) }, 683 { RiscV64Registers.X13, new CPURegister(13, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X13", "A3" }) }, 684 { RiscV64Registers.X14, new CPURegister(14, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X14", "A4" }) }, 685 { RiscV64Registers.X15, new CPURegister(15, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X15", "A5" }) }, 686 { RiscV64Registers.X16, new CPURegister(16, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X16", "A6" }) }, 687 { RiscV64Registers.X17, new CPURegister(17, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X17", "A7" }) }, 688 { RiscV64Registers.X18, new CPURegister(18, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X18", "S2" }) }, 689 { RiscV64Registers.X19, new CPURegister(19, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X19", "S3" }) }, 690 { RiscV64Registers.X20, new CPURegister(20, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X20", "S4" }) }, 691 { RiscV64Registers.X21, new CPURegister(21, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X21", "S5" }) }, 692 { RiscV64Registers.X22, new CPURegister(22, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X22", "S6" }) }, 693 { RiscV64Registers.X23, new CPURegister(23, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X23", "S7" }) }, 694 { RiscV64Registers.X24, new CPURegister(24, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X24", "S8" }) }, 695 { RiscV64Registers.X25, new CPURegister(25, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X25", "S9" }) }, 696 { RiscV64Registers.X26, new CPURegister(26, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X26", "S10" }) }, 697 { RiscV64Registers.X27, new CPURegister(27, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X27", "S11" }) }, 698 { RiscV64Registers.X28, new CPURegister(28, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X28", "T3" }) }, 699 { RiscV64Registers.X29, new CPURegister(29, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X29", "T4" }) }, 700 { RiscV64Registers.X30, new CPURegister(30, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X30", "T5" }) }, 701 { RiscV64Registers.X31, new CPURegister(31, 64, isGeneral: true, isReadonly: false, aliases: new [] { "X31", "T6" }) }, 702 { RiscV64Registers.PC, new CPURegister(32, 64, isGeneral: true, isReadonly: false, aliases: new [] { "PC" }) }, 703 { RiscV64Registers.F0, new CPURegister(33, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F0" }) }, 704 { RiscV64Registers.F1, new CPURegister(34, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F1" }) }, 705 { RiscV64Registers.F2, new CPURegister(35, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F2" }) }, 706 { RiscV64Registers.F3, new CPURegister(36, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F3" }) }, 707 { RiscV64Registers.F4, new CPURegister(37, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F4" }) }, 708 { RiscV64Registers.F5, new CPURegister(38, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F5" }) }, 709 { RiscV64Registers.F6, new CPURegister(39, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F6" }) }, 710 { RiscV64Registers.F7, new CPURegister(40, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F7" }) }, 711 { RiscV64Registers.F8, new CPURegister(41, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F8" }) }, 712 { RiscV64Registers.F9, new CPURegister(42, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F9" }) }, 713 { RiscV64Registers.F10, new CPURegister(43, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F10" }) }, 714 { RiscV64Registers.F11, new CPURegister(44, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F11" }) }, 715 { RiscV64Registers.F12, new CPURegister(45, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F12" }) }, 716 { RiscV64Registers.F13, new CPURegister(46, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F13" }) }, 717 { RiscV64Registers.F14, new CPURegister(47, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F14" }) }, 718 { RiscV64Registers.F15, new CPURegister(48, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F15" }) }, 719 { RiscV64Registers.F16, new CPURegister(49, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F16" }) }, 720 { RiscV64Registers.F17, new CPURegister(50, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F17" }) }, 721 { RiscV64Registers.F18, new CPURegister(51, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F18" }) }, 722 { RiscV64Registers.F19, new CPURegister(52, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F19" }) }, 723 { RiscV64Registers.F20, new CPURegister(53, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F20" }) }, 724 { RiscV64Registers.F21, new CPURegister(54, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F21" }) }, 725 { RiscV64Registers.F22, new CPURegister(55, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F22" }) }, 726 { RiscV64Registers.F23, new CPURegister(56, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F23" }) }, 727 { RiscV64Registers.F24, new CPURegister(57, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F24" }) }, 728 { RiscV64Registers.F25, new CPURegister(58, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F25" }) }, 729 { RiscV64Registers.F26, new CPURegister(59, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F26" }) }, 730 { RiscV64Registers.F27, new CPURegister(60, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F27" }) }, 731 { RiscV64Registers.F28, new CPURegister(61, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F28" }) }, 732 { RiscV64Registers.F29, new CPURegister(62, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F29" }) }, 733 { RiscV64Registers.F30, new CPURegister(63, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F30" }) }, 734 { RiscV64Registers.F31, new CPURegister(64, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F31" }) }, 735 { RiscV64Registers.VSTART, new CPURegister(101, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VSTART" }) }, 736 { RiscV64Registers.VXSAT, new CPURegister(102, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VXSAT" }) }, 737 { RiscV64Registers.VXRM, new CPURegister(103, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VXRM" }) }, 738 { RiscV64Registers.VCSR, new CPURegister(104, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VCSR" }) }, 739 { RiscV64Registers.SSTATUS, new CPURegister(321, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SSTATUS" }) }, 740 { RiscV64Registers.SIE, new CPURegister(325, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SIE" }) }, 741 { RiscV64Registers.STVEC, new CPURegister(326, 64, isGeneral: false, isReadonly: false, aliases: new [] { "STVEC" }) }, 742 { RiscV64Registers.SSCRATCH, new CPURegister(385, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SSCRATCH" }) }, 743 { RiscV64Registers.SEPC, new CPURegister(386, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SEPC" }) }, 744 { RiscV64Registers.SCAUSE, new CPURegister(387, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SCAUSE" }) }, 745 { RiscV64Registers.STVAL, new CPURegister(388, 64, isGeneral: false, isReadonly: false, aliases: new [] { "STVAL" }) }, 746 { RiscV64Registers.SIP, new CPURegister(389, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SIP" }) }, 747 { RiscV64Registers.SATP, new CPURegister(449, 64, isGeneral: false, isReadonly: false, aliases: new [] { "SATP", "SPTBR" }) }, 748 { RiscV64Registers.MSTATUS, new CPURegister(833, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MSTATUS" }) }, 749 { RiscV64Registers.MISA, new CPURegister(834, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MISA" }) }, 750 { RiscV64Registers.MEDELEG, new CPURegister(835, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MEDELEG" }) }, 751 { RiscV64Registers.MIDELEG, new CPURegister(836, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MIDELEG" }) }, 752 { RiscV64Registers.MIE, new CPURegister(837, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MIE" }) }, 753 { RiscV64Registers.MTVEC, new CPURegister(838, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MTVEC" }) }, 754 { RiscV64Registers.MSCRATCH, new CPURegister(897, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MSCRATCH" }) }, 755 { RiscV64Registers.MEPC, new CPURegister(898, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MEPC" }) }, 756 { RiscV64Registers.MCAUSE, new CPURegister(899, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MCAUSE" }) }, 757 { RiscV64Registers.MTVAL, new CPURegister(900, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MTVAL" }) }, 758 { RiscV64Registers.MIP, new CPURegister(901, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MIP" }) }, 759 { RiscV64Registers.MSECCFG, new CPURegister(1863, 64, isGeneral: false, isReadonly: false, aliases: new [] { "MSECCFG" }) }, 760 { RiscV64Registers.VL, new CPURegister(3104, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VL" }) }, 761 { RiscV64Registers.VTYPE, new CPURegister(3105, 64, isGeneral: false, isReadonly: false, aliases: new [] { "VTYPE" }) }, 762 { RiscV64Registers.VLENB, new CPURegister(3106, 64, isGeneral: false, isReadonly: true, aliases: new [] { "VLENB" }) }, 763 { RiscV64Registers.PRIV, new CPURegister(4161, 64, isGeneral: false, isReadonly: false, aliases: new [] { "PRIV" }) }, 764 }; 765 } 766 767 public enum RiscV64Registers 768 { 769 ZERO = 0, 770 RA = 1, 771 SP = 2, 772 GP = 3, 773 TP = 4, 774 FP = 8, 775 PC = 32, 776 SSTATUS = 321, 777 SIE = 325, 778 STVEC = 326, 779 SSCRATCH = 385, 780 SEPC = 386, 781 SCAUSE = 387, 782 STVAL = 388, 783 SIP = 389, 784 SATP = 449, 785 SPTBR = 449, 786 MSTATUS = 833, 787 MISA = 834, 788 MEDELEG = 835, 789 MIDELEG = 836, 790 MIE = 837, 791 MTVEC = 838, 792 MSCRATCH = 897, 793 MEPC = 898, 794 MCAUSE = 899, 795 MTVAL = 900, 796 MIP = 901, 797 PRIV = 4161, 798 VSTART = 101, 799 VXSAT = 102, 800 VXRM = 103, 801 VCSR = 104, 802 MSECCFG = 1863, 803 VL = 3104, 804 VTYPE = 3105, 805 VLENB = 3106, 806 X0 = 0, 807 X1 = 1, 808 X2 = 2, 809 X3 = 3, 810 X4 = 4, 811 X5 = 5, 812 X6 = 6, 813 X7 = 7, 814 X8 = 8, 815 X9 = 9, 816 X10 = 10, 817 X11 = 11, 818 X12 = 12, 819 X13 = 13, 820 X14 = 14, 821 X15 = 15, 822 X16 = 16, 823 X17 = 17, 824 X18 = 18, 825 X19 = 19, 826 X20 = 20, 827 X21 = 21, 828 X22 = 22, 829 X23 = 23, 830 X24 = 24, 831 X25 = 25, 832 X26 = 26, 833 X27 = 27, 834 X28 = 28, 835 X29 = 29, 836 X30 = 30, 837 X31 = 31, 838 T0 = 5, 839 T1 = 6, 840 T2 = 7, 841 T3 = 28, 842 T4 = 29, 843 T5 = 30, 844 T6 = 31, 845 S0 = 8, 846 S1 = 9, 847 S2 = 18, 848 S3 = 19, 849 S4 = 20, 850 S5 = 21, 851 S6 = 22, 852 S7 = 23, 853 S8 = 24, 854 S9 = 25, 855 S10 = 26, 856 S11 = 27, 857 A0 = 10, 858 A1 = 11, 859 A2 = 12, 860 A3 = 13, 861 A4 = 14, 862 A5 = 15, 863 A6 = 16, 864 A7 = 17, 865 F0 = 33, 866 F1 = 34, 867 F2 = 35, 868 F3 = 36, 869 F4 = 37, 870 F5 = 38, 871 F6 = 39, 872 F7 = 40, 873 F8 = 41, 874 F9 = 42, 875 F10 = 43, 876 F11 = 44, 877 F12 = 45, 878 F13 = 46, 879 F14 = 47, 880 F15 = 48, 881 F16 = 49, 882 F17 = 50, 883 F18 = 51, 884 F19 = 52, 885 F20 = 53, 886 F21 = 54, 887 F22 = 55, 888 F23 = 56, 889 F24 = 57, 890 F25 = 58, 891 F26 = 59, 892 F27 = 60, 893 F28 = 61, 894 F29 = 62, 895 F30 = 63, 896 F31 = 64, 897 } 898 } 899
