1 /******************************************************** 2 * 3 * Warning! 4 * This file was generated automatically. 5 * Please do not edit. Changes should be made in the 6 * appropriate *.tt file. 7 * 8 */ 9 using System; 10 using System.Linq; 11 using System.Collections.Generic; 12 using Antmicro.Renode.Peripherals.CPU.Registers; 13 using Antmicro.Renode.Utilities.Binding; 14 using Antmicro.Renode.Exceptions; 15 16 namespace Antmicro.Renode.Peripherals.CPU 17 { 18 public partial class RiscV32 19 { SetRegister(int register, RegisterValue value)20 public override void SetRegister(int register, RegisterValue value) 21 { 22 if(!mapping.TryGetValue((RiscV32Registers)register, out var r)) 23 { 24 if(TrySetNonMappedRegister(register, value)) 25 { 26 return; 27 } 28 throw new RecoverableException($"Wrong register index: {register}"); 29 } 30 if(r.IsReadonly) 31 { 32 throw new RecoverableException($"The '{(RiscV32Registers)register}' register is read-only."); 33 } 34 35 switch(r.Width) 36 { 37 case 32: 38 SetRegisterValue32(r.Index, checked((uint)value)); 39 break; 40 case 64: 41 SetRegisterValue64(r.Index, checked((ulong)value)); 42 break; 43 default: 44 throw new ArgumentException($"Unsupported register width: {r.Width}"); 45 } 46 } 47 GetRegister(int register)48 public override RegisterValue GetRegister(int register) 49 { 50 if(!mapping.TryGetValue((RiscV32Registers)register, out var r)) 51 { 52 if(TryGetNonMappedRegister(register, out var value)) 53 { 54 return value; 55 } 56 throw new RecoverableException($"Wrong register index: {register}"); 57 } 58 switch(r.Width) 59 { 60 case 32: 61 return GetRegisterValue32(r.Index); 62 case 64: 63 return GetRegisterValue64(r.Index); 64 default: 65 throw new ArgumentException($"Unsupported register width: {r.Width}"); 66 } 67 } 68 GetRegisters()69 public override IEnumerable<CPURegister> GetRegisters() 70 { 71 return mapping.Values.Concat(GetNonMappedRegisters()).OrderBy(x => x.Index); 72 } 73 74 [Register] 75 public RegisterValue ZERO 76 { 77 get 78 { 79 return GetRegisterValue32((int)RiscV32Registers.ZERO); 80 } 81 set 82 { 83 SetRegisterValue32((int)RiscV32Registers.ZERO, value); 84 } 85 } 86 [Register] 87 public RegisterValue RA 88 { 89 get 90 { 91 return GetRegisterValue32((int)RiscV32Registers.RA); 92 } 93 set 94 { 95 SetRegisterValue32((int)RiscV32Registers.RA, value); 96 } 97 } 98 [Register] 99 public RegisterValue SP 100 { 101 get 102 { 103 return GetRegisterValue32((int)RiscV32Registers.SP); 104 } 105 set 106 { 107 SetRegisterValue32((int)RiscV32Registers.SP, value); 108 } 109 } 110 [Register] 111 public RegisterValue GP 112 { 113 get 114 { 115 return GetRegisterValue32((int)RiscV32Registers.GP); 116 } 117 set 118 { 119 SetRegisterValue32((int)RiscV32Registers.GP, value); 120 } 121 } 122 [Register] 123 public RegisterValue TP 124 { 125 get 126 { 127 return GetRegisterValue32((int)RiscV32Registers.TP); 128 } 129 set 130 { 131 SetRegisterValue32((int)RiscV32Registers.TP, value); 132 } 133 } 134 [Register] 135 public RegisterValue FP 136 { 137 get 138 { 139 return GetRegisterValue32((int)RiscV32Registers.FP); 140 } 141 set 142 { 143 SetRegisterValue32((int)RiscV32Registers.FP, value); 144 } 145 } 146 [Register] 147 public override RegisterValue PC 148 { 149 get 150 { 151 return GetRegisterValue32((int)RiscV32Registers.PC); 152 } 153 set 154 { 155 value = BeforePCWrite(value); 156 SetRegisterValue32((int)RiscV32Registers.PC, value); 157 } 158 } 159 [Register] 160 public RegisterValue SSTATUS 161 { 162 get 163 { 164 return GetRegisterValue32((int)RiscV32Registers.SSTATUS); 165 } 166 set 167 { 168 SetRegisterValue32((int)RiscV32Registers.SSTATUS, value); 169 } 170 } 171 [Register] 172 public RegisterValue SIE 173 { 174 get 175 { 176 return GetRegisterValue32((int)RiscV32Registers.SIE); 177 } 178 set 179 { 180 SetRegisterValue32((int)RiscV32Registers.SIE, value); 181 } 182 } 183 [Register] 184 public RegisterValue STVEC 185 { 186 get 187 { 188 return GetRegisterValue32((int)RiscV32Registers.STVEC); 189 } 190 set 191 { 192 value = BeforeSTVECWrite(value); 193 SetRegisterValue32((int)RiscV32Registers.STVEC, value); 194 } 195 } 196 [Register] 197 public RegisterValue SSCRATCH 198 { 199 get 200 { 201 return GetRegisterValue32((int)RiscV32Registers.SSCRATCH); 202 } 203 set 204 { 205 SetRegisterValue32((int)RiscV32Registers.SSCRATCH, value); 206 } 207 } 208 [Register] 209 public RegisterValue SEPC 210 { 211 get 212 { 213 return GetRegisterValue32((int)RiscV32Registers.SEPC); 214 } 215 set 216 { 217 SetRegisterValue32((int)RiscV32Registers.SEPC, value); 218 } 219 } 220 [Register] 221 public RegisterValue SCAUSE 222 { 223 get 224 { 225 return GetRegisterValue32((int)RiscV32Registers.SCAUSE); 226 } 227 set 228 { 229 SetRegisterValue32((int)RiscV32Registers.SCAUSE, value); 230 } 231 } 232 [Register] 233 public RegisterValue STVAL 234 { 235 get 236 { 237 return GetRegisterValue32((int)RiscV32Registers.STVAL); 238 } 239 set 240 { 241 SetRegisterValue32((int)RiscV32Registers.STVAL, value); 242 } 243 } 244 [Register] 245 public RegisterValue SIP 246 { 247 get 248 { 249 return GetRegisterValue32((int)RiscV32Registers.SIP); 250 } 251 set 252 { 253 SetRegisterValue32((int)RiscV32Registers.SIP, value); 254 } 255 } 256 [Register] 257 public RegisterValue SATP 258 { 259 get 260 { 261 return GetRegisterValue32((int)RiscV32Registers.SATP); 262 } 263 set 264 { 265 SetRegisterValue32((int)RiscV32Registers.SATP, value); 266 } 267 } 268 [Register] 269 public RegisterValue SPTBR 270 { 271 get 272 { 273 return GetRegisterValue32((int)RiscV32Registers.SPTBR); 274 } 275 set 276 { 277 SetRegisterValue32((int)RiscV32Registers.SPTBR, value); 278 } 279 } 280 [Register] 281 public RegisterValue MSTATUS 282 { 283 get 284 { 285 return GetRegisterValue32((int)RiscV32Registers.MSTATUS); 286 } 287 set 288 { 289 SetRegisterValue32((int)RiscV32Registers.MSTATUS, value); 290 } 291 } 292 [Register] 293 public RegisterValue MISA 294 { 295 get 296 { 297 return GetRegisterValue32((int)RiscV32Registers.MISA); 298 } 299 set 300 { 301 SetRegisterValue32((int)RiscV32Registers.MISA, value); 302 } 303 } 304 [Register] 305 public RegisterValue MEDELEG 306 { 307 get 308 { 309 return GetRegisterValue32((int)RiscV32Registers.MEDELEG); 310 } 311 set 312 { 313 SetRegisterValue32((int)RiscV32Registers.MEDELEG, value); 314 } 315 } 316 [Register] 317 public RegisterValue MIDELEG 318 { 319 get 320 { 321 return GetRegisterValue32((int)RiscV32Registers.MIDELEG); 322 } 323 set 324 { 325 SetRegisterValue32((int)RiscV32Registers.MIDELEG, value); 326 } 327 } 328 [Register] 329 public RegisterValue MIE 330 { 331 get 332 { 333 return GetRegisterValue32((int)RiscV32Registers.MIE); 334 } 335 set 336 { 337 SetRegisterValue32((int)RiscV32Registers.MIE, value); 338 } 339 } 340 [Register] 341 public RegisterValue MTVEC 342 { 343 get 344 { 345 return GetRegisterValue32((int)RiscV32Registers.MTVEC); 346 } 347 set 348 { 349 value = BeforeMTVECWrite(value); 350 SetRegisterValue32((int)RiscV32Registers.MTVEC, value); 351 } 352 } 353 [Register] 354 public RegisterValue MSCRATCH 355 { 356 get 357 { 358 return GetRegisterValue32((int)RiscV32Registers.MSCRATCH); 359 } 360 set 361 { 362 SetRegisterValue32((int)RiscV32Registers.MSCRATCH, value); 363 } 364 } 365 [Register] 366 public RegisterValue MEPC 367 { 368 get 369 { 370 return GetRegisterValue32((int)RiscV32Registers.MEPC); 371 } 372 set 373 { 374 SetRegisterValue32((int)RiscV32Registers.MEPC, value); 375 } 376 } 377 [Register] 378 public RegisterValue MCAUSE 379 { 380 get 381 { 382 return GetRegisterValue32((int)RiscV32Registers.MCAUSE); 383 } 384 set 385 { 386 SetRegisterValue32((int)RiscV32Registers.MCAUSE, value); 387 } 388 } 389 [Register] 390 public RegisterValue MTVAL 391 { 392 get 393 { 394 return GetRegisterValue32((int)RiscV32Registers.MTVAL); 395 } 396 set 397 { 398 SetRegisterValue32((int)RiscV32Registers.MTVAL, value); 399 } 400 } 401 [Register] 402 public RegisterValue MIP 403 { 404 get 405 { 406 return GetRegisterValue32((int)RiscV32Registers.MIP); 407 } 408 set 409 { 410 SetRegisterValue32((int)RiscV32Registers.MIP, value); 411 } 412 } 413 [Register] 414 public RegisterValue MSECCFG 415 { 416 get 417 { 418 return GetRegisterValue32((int)RiscV32Registers.MSECCFG); 419 } 420 set 421 { 422 SetRegisterValue32((int)RiscV32Registers.MSECCFG, value); 423 } 424 } 425 [Register] 426 public RegisterValue PRIV 427 { 428 get 429 { 430 return GetRegisterValue32((int)RiscV32Registers.PRIV); 431 } 432 set 433 { 434 SetRegisterValue32((int)RiscV32Registers.PRIV, value); 435 } 436 } 437 [Register] 438 public RegisterValue VSTART 439 { 440 get 441 { 442 BeforeVectorExtensionRegisterRead(); 443 return GetRegisterValue32((int)RiscV32Registers.VSTART); 444 } 445 set 446 { 447 value = BeforeVectorExtensionRegisterWrite(value); 448 SetRegisterValue32((int)RiscV32Registers.VSTART, value); 449 } 450 } 451 [Register] 452 public RegisterValue VXSAT 453 { 454 get 455 { 456 BeforeVectorExtensionRegisterRead(); 457 return GetRegisterValue32((int)RiscV32Registers.VXSAT); 458 } 459 set 460 { 461 value = BeforeVectorExtensionRegisterWrite(value); 462 SetRegisterValue32((int)RiscV32Registers.VXSAT, value); 463 } 464 } 465 [Register] 466 public RegisterValue VXRM 467 { 468 get 469 { 470 BeforeVectorExtensionRegisterRead(); 471 return GetRegisterValue32((int)RiscV32Registers.VXRM); 472 } 473 set 474 { 475 value = BeforeVectorExtensionRegisterWrite(value); 476 SetRegisterValue32((int)RiscV32Registers.VXRM, value); 477 } 478 } 479 [Register] 480 public RegisterValue VCSR 481 { 482 get 483 { 484 BeforeVectorExtensionRegisterRead(); 485 return GetRegisterValue32((int)RiscV32Registers.VCSR); 486 } 487 set 488 { 489 value = BeforeVectorExtensionRegisterWrite(value); 490 SetRegisterValue32((int)RiscV32Registers.VCSR, value); 491 } 492 } 493 [Register] 494 public RegisterValue VL 495 { 496 get 497 { 498 BeforeVectorExtensionRegisterRead(); 499 return GetRegisterValue32((int)RiscV32Registers.VL); 500 } 501 set 502 { 503 value = BeforeVectorExtensionRegisterWrite(value); 504 SetRegisterValue32((int)RiscV32Registers.VL, value); 505 } 506 } 507 [Register] 508 public RegisterValue VTYPE 509 { 510 get 511 { 512 BeforeVectorExtensionRegisterRead(); 513 return GetRegisterValue32((int)RiscV32Registers.VTYPE); 514 } 515 set 516 { 517 value = BeforeVectorExtensionRegisterWrite(value); 518 SetRegisterValue32((int)RiscV32Registers.VTYPE, value); 519 } 520 } 521 [Register] 522 public RegisterValue VLENB 523 { 524 get 525 { 526 BeforeVectorExtensionRegisterRead(); 527 return GetRegisterValue32((int)RiscV32Registers.VLENB); 528 } 529 set 530 { 531 value = BeforeVectorExtensionRegisterWrite(value); 532 SetRegisterValue32((int)RiscV32Registers.VLENB, value); 533 } 534 } 535 public RegistersGroup X { get; private set; } 536 public RegistersGroup T { get; private set; } 537 public RegistersGroup S { get; private set; } 538 public RegistersGroup A { get; private set; } 539 public RegistersGroup F { get; private set; } 540 InitializeRegisters()541 protected override void InitializeRegisters() 542 { 543 var indexValueMapX = new Dictionary<int, RiscV32Registers> 544 { 545 { 0, RiscV32Registers.X0 }, 546 { 1, RiscV32Registers.X1 }, 547 { 2, RiscV32Registers.X2 }, 548 { 3, RiscV32Registers.X3 }, 549 { 4, RiscV32Registers.X4 }, 550 { 5, RiscV32Registers.X5 }, 551 { 6, RiscV32Registers.X6 }, 552 { 7, RiscV32Registers.X7 }, 553 { 8, RiscV32Registers.X8 }, 554 { 9, RiscV32Registers.X9 }, 555 { 10, RiscV32Registers.X10 }, 556 { 11, RiscV32Registers.X11 }, 557 { 12, RiscV32Registers.X12 }, 558 { 13, RiscV32Registers.X13 }, 559 { 14, RiscV32Registers.X14 }, 560 { 15, RiscV32Registers.X15 }, 561 { 16, RiscV32Registers.X16 }, 562 { 17, RiscV32Registers.X17 }, 563 { 18, RiscV32Registers.X18 }, 564 { 19, RiscV32Registers.X19 }, 565 { 20, RiscV32Registers.X20 }, 566 { 21, RiscV32Registers.X21 }, 567 { 22, RiscV32Registers.X22 }, 568 { 23, RiscV32Registers.X23 }, 569 { 24, RiscV32Registers.X24 }, 570 { 25, RiscV32Registers.X25 }, 571 { 26, RiscV32Registers.X26 }, 572 { 27, RiscV32Registers.X27 }, 573 { 28, RiscV32Registers.X28 }, 574 { 29, RiscV32Registers.X29 }, 575 { 30, RiscV32Registers.X30 }, 576 { 31, RiscV32Registers.X31 }, 577 }; 578 X = new RegistersGroup( 579 indexValueMapX.Keys, 580 i => GetRegister((int)indexValueMapX[i]), 581 (i, v) => SetRegister((int)indexValueMapX[i], v)); 582 583 var indexValueMapT = new Dictionary<int, RiscV32Registers> 584 { 585 { 0, RiscV32Registers.T0 }, 586 { 1, RiscV32Registers.T1 }, 587 { 2, RiscV32Registers.T2 }, 588 { 3, RiscV32Registers.T3 }, 589 { 4, RiscV32Registers.T4 }, 590 { 5, RiscV32Registers.T5 }, 591 { 6, RiscV32Registers.T6 }, 592 }; 593 T = new RegistersGroup( 594 indexValueMapT.Keys, 595 i => GetRegister((int)indexValueMapT[i]), 596 (i, v) => SetRegister((int)indexValueMapT[i], v)); 597 598 var indexValueMapS = new Dictionary<int, RiscV32Registers> 599 { 600 { 0, RiscV32Registers.S0 }, 601 { 1, RiscV32Registers.S1 }, 602 { 2, RiscV32Registers.S2 }, 603 { 3, RiscV32Registers.S3 }, 604 { 4, RiscV32Registers.S4 }, 605 { 5, RiscV32Registers.S5 }, 606 { 6, RiscV32Registers.S6 }, 607 { 7, RiscV32Registers.S7 }, 608 { 8, RiscV32Registers.S8 }, 609 { 9, RiscV32Registers.S9 }, 610 { 10, RiscV32Registers.S10 }, 611 { 11, RiscV32Registers.S11 }, 612 }; 613 S = new RegistersGroup( 614 indexValueMapS.Keys, 615 i => GetRegister((int)indexValueMapS[i]), 616 (i, v) => SetRegister((int)indexValueMapS[i], v)); 617 618 var indexValueMapA = new Dictionary<int, RiscV32Registers> 619 { 620 { 0, RiscV32Registers.A0 }, 621 { 1, RiscV32Registers.A1 }, 622 { 2, RiscV32Registers.A2 }, 623 { 3, RiscV32Registers.A3 }, 624 { 4, RiscV32Registers.A4 }, 625 { 5, RiscV32Registers.A5 }, 626 { 6, RiscV32Registers.A6 }, 627 { 7, RiscV32Registers.A7 }, 628 }; 629 A = new RegistersGroup( 630 indexValueMapA.Keys, 631 i => GetRegister((int)indexValueMapA[i]), 632 (i, v) => SetRegister((int)indexValueMapA[i], v)); 633 634 var indexValueMapF = new Dictionary<int, RiscV32Registers> 635 { 636 { 0, RiscV32Registers.F0 }, 637 { 1, RiscV32Registers.F1 }, 638 { 2, RiscV32Registers.F2 }, 639 { 3, RiscV32Registers.F3 }, 640 { 4, RiscV32Registers.F4 }, 641 { 5, RiscV32Registers.F5 }, 642 { 6, RiscV32Registers.F6 }, 643 { 7, RiscV32Registers.F7 }, 644 { 8, RiscV32Registers.F8 }, 645 { 9, RiscV32Registers.F9 }, 646 { 10, RiscV32Registers.F10 }, 647 { 11, RiscV32Registers.F11 }, 648 { 12, RiscV32Registers.F12 }, 649 { 13, RiscV32Registers.F13 }, 650 { 14, RiscV32Registers.F14 }, 651 { 15, RiscV32Registers.F15 }, 652 { 16, RiscV32Registers.F16 }, 653 { 17, RiscV32Registers.F17 }, 654 { 18, RiscV32Registers.F18 }, 655 { 19, RiscV32Registers.F19 }, 656 { 20, RiscV32Registers.F20 }, 657 { 21, RiscV32Registers.F21 }, 658 { 22, RiscV32Registers.F22 }, 659 { 23, RiscV32Registers.F23 }, 660 { 24, RiscV32Registers.F24 }, 661 { 25, RiscV32Registers.F25 }, 662 { 26, RiscV32Registers.F26 }, 663 { 27, RiscV32Registers.F27 }, 664 { 28, RiscV32Registers.F28 }, 665 { 29, RiscV32Registers.F29 }, 666 { 30, RiscV32Registers.F30 }, 667 { 31, RiscV32Registers.F31 }, 668 }; 669 F = new RegistersGroup( 670 indexValueMapF.Keys, 671 i => GetRegister((int)indexValueMapF[i]), 672 (i, v) => SetRegister((int)indexValueMapF[i], v)); 673 674 } 675 676 // 649: Field '...' is never assigned to, and will always have its default value null 677 #pragma warning disable 649 678 679 [Import(Name = "tlib_set_register_value_32")] 680 protected Action<int, uint> SetRegisterValue32; 681 [Import(Name = "tlib_get_register_value_32")] 682 protected Func<int, uint> GetRegisterValue32; 683 684 #pragma warning restore 649 685 686 // 649: Field '...' is never assigned to, and will always have its default value null 687 #pragma warning disable 649 688 689 [Import(Name = "tlib_set_register_value_64")] 690 protected Action<int, ulong> SetRegisterValue64; 691 [Import(Name = "tlib_get_register_value_64")] 692 protected Func<int, ulong> GetRegisterValue64; 693 694 #pragma warning restore 649 695 696 private static readonly Dictionary<RiscV32Registers, CPURegister> mapping = new Dictionary<RiscV32Registers, CPURegister> 697 { 698 { RiscV32Registers.ZERO, new CPURegister(0, 32, isGeneral: true, isReadonly: true, aliases: new [] { "ZERO", "X0" }) }, 699 { RiscV32Registers.RA, new CPURegister(1, 32, isGeneral: true, isReadonly: false, aliases: new [] { "RA", "X1" }) }, 700 { RiscV32Registers.SP, new CPURegister(2, 32, isGeneral: true, isReadonly: false, aliases: new [] { "SP", "X2" }) }, 701 { RiscV32Registers.GP, new CPURegister(3, 32, isGeneral: true, isReadonly: false, aliases: new [] { "GP", "X3" }) }, 702 { RiscV32Registers.TP, new CPURegister(4, 32, isGeneral: true, isReadonly: false, aliases: new [] { "TP", "X4" }) }, 703 { RiscV32Registers.X5, new CPURegister(5, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X5", "T0" }) }, 704 { RiscV32Registers.X6, new CPURegister(6, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X6", "T1" }) }, 705 { RiscV32Registers.X7, new CPURegister(7, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X7", "T2" }) }, 706 { RiscV32Registers.FP, new CPURegister(8, 32, isGeneral: true, isReadonly: false, aliases: new [] { "FP", "X8", "S0" }) }, 707 { RiscV32Registers.X9, new CPURegister(9, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X9", "S1" }) }, 708 { RiscV32Registers.X10, new CPURegister(10, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X10", "A0" }) }, 709 { RiscV32Registers.X11, new CPURegister(11, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X11", "A1" }) }, 710 { RiscV32Registers.X12, new CPURegister(12, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X12", "A2" }) }, 711 { RiscV32Registers.X13, new CPURegister(13, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X13", "A3" }) }, 712 { RiscV32Registers.X14, new CPURegister(14, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X14", "A4" }) }, 713 { RiscV32Registers.X15, new CPURegister(15, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X15", "A5" }) }, 714 { RiscV32Registers.X16, new CPURegister(16, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X16", "A6" }) }, 715 { RiscV32Registers.X17, new CPURegister(17, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X17", "A7" }) }, 716 { RiscV32Registers.X18, new CPURegister(18, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X18", "S2" }) }, 717 { RiscV32Registers.X19, new CPURegister(19, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X19", "S3" }) }, 718 { RiscV32Registers.X20, new CPURegister(20, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X20", "S4" }) }, 719 { RiscV32Registers.X21, new CPURegister(21, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X21", "S5" }) }, 720 { RiscV32Registers.X22, new CPURegister(22, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X22", "S6" }) }, 721 { RiscV32Registers.X23, new CPURegister(23, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X23", "S7" }) }, 722 { RiscV32Registers.X24, new CPURegister(24, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X24", "S8" }) }, 723 { RiscV32Registers.X25, new CPURegister(25, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X25", "S9" }) }, 724 { RiscV32Registers.X26, new CPURegister(26, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X26", "S10" }) }, 725 { RiscV32Registers.X27, new CPURegister(27, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X27", "S11" }) }, 726 { RiscV32Registers.X28, new CPURegister(28, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X28", "T3" }) }, 727 { RiscV32Registers.X29, new CPURegister(29, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X29", "T4" }) }, 728 { RiscV32Registers.X30, new CPURegister(30, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X30", "T5" }) }, 729 { RiscV32Registers.X31, new CPURegister(31, 32, isGeneral: true, isReadonly: false, aliases: new [] { "X31", "T6" }) }, 730 { RiscV32Registers.PC, new CPURegister(32, 32, isGeneral: true, isReadonly: false, aliases: new [] { "PC" }) }, 731 { RiscV32Registers.F0, new CPURegister(33, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F0" }) }, 732 { RiscV32Registers.F1, new CPURegister(34, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F1" }) }, 733 { RiscV32Registers.F2, new CPURegister(35, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F2" }) }, 734 { RiscV32Registers.F3, new CPURegister(36, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F3" }) }, 735 { RiscV32Registers.F4, new CPURegister(37, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F4" }) }, 736 { RiscV32Registers.F5, new CPURegister(38, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F5" }) }, 737 { RiscV32Registers.F6, new CPURegister(39, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F6" }) }, 738 { RiscV32Registers.F7, new CPURegister(40, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F7" }) }, 739 { RiscV32Registers.F8, new CPURegister(41, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F8" }) }, 740 { RiscV32Registers.F9, new CPURegister(42, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F9" }) }, 741 { RiscV32Registers.F10, new CPURegister(43, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F10" }) }, 742 { RiscV32Registers.F11, new CPURegister(44, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F11" }) }, 743 { RiscV32Registers.F12, new CPURegister(45, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F12" }) }, 744 { RiscV32Registers.F13, new CPURegister(46, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F13" }) }, 745 { RiscV32Registers.F14, new CPURegister(47, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F14" }) }, 746 { RiscV32Registers.F15, new CPURegister(48, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F15" }) }, 747 { RiscV32Registers.F16, new CPURegister(49, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F16" }) }, 748 { RiscV32Registers.F17, new CPURegister(50, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F17" }) }, 749 { RiscV32Registers.F18, new CPURegister(51, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F18" }) }, 750 { RiscV32Registers.F19, new CPURegister(52, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F19" }) }, 751 { RiscV32Registers.F20, new CPURegister(53, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F20" }) }, 752 { RiscV32Registers.F21, new CPURegister(54, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F21" }) }, 753 { RiscV32Registers.F22, new CPURegister(55, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F22" }) }, 754 { RiscV32Registers.F23, new CPURegister(56, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F23" }) }, 755 { RiscV32Registers.F24, new CPURegister(57, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F24" }) }, 756 { RiscV32Registers.F25, new CPURegister(58, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F25" }) }, 757 { RiscV32Registers.F26, new CPURegister(59, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F26" }) }, 758 { RiscV32Registers.F27, new CPURegister(60, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F27" }) }, 759 { RiscV32Registers.F28, new CPURegister(61, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F28" }) }, 760 { RiscV32Registers.F29, new CPURegister(62, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F29" }) }, 761 { RiscV32Registers.F30, new CPURegister(63, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F30" }) }, 762 { RiscV32Registers.F31, new CPURegister(64, 64, isGeneral: false, isReadonly: false, aliases: new [] { "F31" }) }, 763 { RiscV32Registers.VSTART, new CPURegister(101, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VSTART" }) }, 764 { RiscV32Registers.VXSAT, new CPURegister(102, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VXSAT" }) }, 765 { RiscV32Registers.VXRM, new CPURegister(103, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VXRM" }) }, 766 { RiscV32Registers.VCSR, new CPURegister(104, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VCSR" }) }, 767 { RiscV32Registers.SSTATUS, new CPURegister(321, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SSTATUS" }) }, 768 { RiscV32Registers.SIE, new CPURegister(325, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SIE" }) }, 769 { RiscV32Registers.STVEC, new CPURegister(326, 32, isGeneral: false, isReadonly: false, aliases: new [] { "STVEC" }) }, 770 { RiscV32Registers.SSCRATCH, new CPURegister(385, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SSCRATCH" }) }, 771 { RiscV32Registers.SEPC, new CPURegister(386, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SEPC" }) }, 772 { RiscV32Registers.SCAUSE, new CPURegister(387, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SCAUSE" }) }, 773 { RiscV32Registers.STVAL, new CPURegister(388, 32, isGeneral: false, isReadonly: false, aliases: new [] { "STVAL" }) }, 774 { RiscV32Registers.SIP, new CPURegister(389, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SIP" }) }, 775 { RiscV32Registers.SATP, new CPURegister(449, 32, isGeneral: false, isReadonly: false, aliases: new [] { "SATP", "SPTBR" }) }, 776 { RiscV32Registers.MSTATUS, new CPURegister(833, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MSTATUS" }) }, 777 { RiscV32Registers.MISA, new CPURegister(834, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MISA" }) }, 778 { RiscV32Registers.MEDELEG, new CPURegister(835, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MEDELEG" }) }, 779 { RiscV32Registers.MIDELEG, new CPURegister(836, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MIDELEG" }) }, 780 { RiscV32Registers.MIE, new CPURegister(837, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MIE" }) }, 781 { RiscV32Registers.MTVEC, new CPURegister(838, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MTVEC" }) }, 782 { RiscV32Registers.MSCRATCH, new CPURegister(897, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MSCRATCH" }) }, 783 { RiscV32Registers.MEPC, new CPURegister(898, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MEPC" }) }, 784 { RiscV32Registers.MCAUSE, new CPURegister(899, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MCAUSE" }) }, 785 { RiscV32Registers.MTVAL, new CPURegister(900, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MTVAL" }) }, 786 { RiscV32Registers.MIP, new CPURegister(901, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MIP" }) }, 787 { RiscV32Registers.MSECCFG, new CPURegister(1863, 32, isGeneral: false, isReadonly: false, aliases: new [] { "MSECCFG" }) }, 788 { RiscV32Registers.VL, new CPURegister(3104, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VL" }) }, 789 { RiscV32Registers.VTYPE, new CPURegister(3105, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VTYPE" }) }, 790 { RiscV32Registers.VLENB, new CPURegister(3106, 32, isGeneral: false, isReadonly: true, aliases: new [] { "VLENB" }) }, 791 { RiscV32Registers.PRIV, new CPURegister(4161, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PRIV" }) }, 792 }; 793 } 794 795 public enum RiscV32Registers 796 { 797 ZERO = 0, 798 RA = 1, 799 SP = 2, 800 GP = 3, 801 TP = 4, 802 FP = 8, 803 PC = 32, 804 SSTATUS = 321, 805 SIE = 325, 806 STVEC = 326, 807 SSCRATCH = 385, 808 SEPC = 386, 809 SCAUSE = 387, 810 STVAL = 388, 811 SIP = 389, 812 SATP = 449, 813 SPTBR = 449, 814 MSTATUS = 833, 815 MISA = 834, 816 MEDELEG = 835, 817 MIDELEG = 836, 818 MIE = 837, 819 MTVEC = 838, 820 MSCRATCH = 897, 821 MEPC = 898, 822 MCAUSE = 899, 823 MTVAL = 900, 824 MIP = 901, 825 MSECCFG = 1863, 826 PRIV = 4161, 827 VSTART = 101, 828 VXSAT = 102, 829 VXRM = 103, 830 VCSR = 104, 831 VL = 3104, 832 VTYPE = 3105, 833 VLENB = 3106, 834 X0 = 0, 835 X1 = 1, 836 X2 = 2, 837 X3 = 3, 838 X4 = 4, 839 X5 = 5, 840 X6 = 6, 841 X7 = 7, 842 X8 = 8, 843 X9 = 9, 844 X10 = 10, 845 X11 = 11, 846 X12 = 12, 847 X13 = 13, 848 X14 = 14, 849 X15 = 15, 850 X16 = 16, 851 X17 = 17, 852 X18 = 18, 853 X19 = 19, 854 X20 = 20, 855 X21 = 21, 856 X22 = 22, 857 X23 = 23, 858 X24 = 24, 859 X25 = 25, 860 X26 = 26, 861 X27 = 27, 862 X28 = 28, 863 X29 = 29, 864 X30 = 30, 865 X31 = 31, 866 T0 = 5, 867 T1 = 6, 868 T2 = 7, 869 T3 = 28, 870 T4 = 29, 871 T5 = 30, 872 T6 = 31, 873 S0 = 8, 874 S1 = 9, 875 S2 = 18, 876 S3 = 19, 877 S4 = 20, 878 S5 = 21, 879 S6 = 22, 880 S7 = 23, 881 S8 = 24, 882 S9 = 25, 883 S10 = 26, 884 S11 = 27, 885 A0 = 10, 886 A1 = 11, 887 A2 = 12, 888 A3 = 13, 889 A4 = 14, 890 A5 = 15, 891 A6 = 16, 892 A7 = 17, 893 F0 = 33, 894 F1 = 34, 895 F2 = 35, 896 F3 = 36, 897 F4 = 37, 898 F5 = 38, 899 F6 = 39, 900 F7 = 40, 901 F8 = 41, 902 F9 = 42, 903 F10 = 43, 904 F11 = 44, 905 F12 = 45, 906 F13 = 46, 907 F14 = 47, 908 F15 = 48, 909 F16 = 49, 910 F17 = 50, 911 F18 = 51, 912 F19 = 52, 913 F20 = 53, 914 F21 = 54, 915 F22 = 55, 916 F23 = 56, 917 F24 = 57, 918 F25 = 58, 919 F26 = 59, 920 F27 = 60, 921 F28 = 61, 922 F29 = 62, 923 F30 = 63, 924 F31 = 64, 925 } 926 } 927
