1 /******************************************************** 2 * 3 * Warning! 4 * This file was generated automatically. 5 * Please do not edit. Changes should be made in the 6 * appropriate *.tt file. 7 * 8 */ 9 using System; 10 using System.Linq; 11 using System.Collections.Generic; 12 using Antmicro.Renode.Peripherals.CPU.Registers; 13 using Antmicro.Renode.Utilities.Binding; 14 using Antmicro.Renode.Exceptions; 15 16 namespace Antmicro.Renode.Peripherals.CPU 17 { 18 public partial class Arm 19 { SetRegister(int register, RegisterValue value)20 public override void SetRegister(int register, RegisterValue value) 21 { 22 if(!mapping.TryGetValue((ArmRegisters)register, out var r)) 23 { 24 throw new RecoverableException($"Wrong register index: {register}"); 25 } 26 27 SetRegisterValue32(r.Index, checked((uint)value)); 28 } 29 GetRegister(int register)30 public override RegisterValue GetRegister(int register) 31 { 32 if(!mapping.TryGetValue((ArmRegisters)register, out var r)) 33 { 34 throw new RecoverableException($"Wrong register index: {register}"); 35 } 36 return GetRegisterValue32(r.Index); 37 } 38 GetRegisters()39 public override IEnumerable<CPURegister> GetRegisters() 40 { 41 return mapping.Values.OrderBy(x => x.Index); 42 } 43 44 [Register] 45 public RegisterValue SP 46 { 47 get 48 { 49 return GetRegisterValue32((int)ArmRegisters.SP); 50 } 51 set 52 { 53 SetRegisterValue32((int)ArmRegisters.SP, value); 54 } 55 } 56 [Register] 57 public RegisterValue LR 58 { 59 get 60 { 61 return GetRegisterValue32((int)ArmRegisters.LR); 62 } 63 set 64 { 65 SetRegisterValue32((int)ArmRegisters.LR, value); 66 } 67 } 68 [Register] 69 public override RegisterValue PC 70 { 71 get 72 { 73 return GetRegisterValue32((int)ArmRegisters.PC); 74 } 75 set 76 { 77 value = BeforePCWrite(value); 78 SetRegisterValue32((int)ArmRegisters.PC, value); 79 } 80 } 81 [Register] 82 public RegisterValue CPSR 83 { 84 get 85 { 86 return GetRegisterValue32((int)ArmRegisters.CPSR); 87 } 88 set 89 { 90 SetRegisterValue32((int)ArmRegisters.CPSR, value); 91 } 92 } 93 public RegistersGroup R { get; private set; } 94 InitializeRegisters()95 protected override void InitializeRegisters() 96 { 97 var indexValueMapR = new Dictionary<int, ArmRegisters> 98 { 99 { 0, ArmRegisters.R0 }, 100 { 1, ArmRegisters.R1 }, 101 { 2, ArmRegisters.R2 }, 102 { 3, ArmRegisters.R3 }, 103 { 4, ArmRegisters.R4 }, 104 { 5, ArmRegisters.R5 }, 105 { 6, ArmRegisters.R6 }, 106 { 7, ArmRegisters.R7 }, 107 { 8, ArmRegisters.R8 }, 108 { 9, ArmRegisters.R9 }, 109 { 10, ArmRegisters.R10 }, 110 { 11, ArmRegisters.R11 }, 111 { 12, ArmRegisters.R12 }, 112 { 13, ArmRegisters.R13 }, 113 { 14, ArmRegisters.R14 }, 114 { 15, ArmRegisters.R15 }, 115 }; 116 R = new RegistersGroup( 117 indexValueMapR.Keys, 118 i => GetRegister((int)indexValueMapR[i]), 119 (i, v) => SetRegister((int)indexValueMapR[i], v)); 120 121 } 122 123 // 649: Field '...' is never assigned to, and will always have its default value null 124 #pragma warning disable 649 125 126 [Import(Name = "tlib_set_register_value_32")] 127 protected Action<int, uint> SetRegisterValue32; 128 [Import(Name = "tlib_get_register_value_32")] 129 protected Func<int, uint> GetRegisterValue32; 130 131 #pragma warning restore 649 132 133 private static readonly Dictionary<ArmRegisters, CPURegister> mapping = new Dictionary<ArmRegisters, CPURegister> 134 { 135 { ArmRegisters.R0, new CPURegister(0, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R0" }) }, 136 { ArmRegisters.R1, new CPURegister(1, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R1" }) }, 137 { ArmRegisters.R2, new CPURegister(2, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R2" }) }, 138 { ArmRegisters.R3, new CPURegister(3, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R3" }) }, 139 { ArmRegisters.R4, new CPURegister(4, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R4" }) }, 140 { ArmRegisters.R5, new CPURegister(5, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R5" }) }, 141 { ArmRegisters.R6, new CPURegister(6, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R6" }) }, 142 { ArmRegisters.R7, new CPURegister(7, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R7" }) }, 143 { ArmRegisters.R8, new CPURegister(8, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R8" }) }, 144 { ArmRegisters.R9, new CPURegister(9, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R9" }) }, 145 { ArmRegisters.R10, new CPURegister(10, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R10" }) }, 146 { ArmRegisters.R11, new CPURegister(11, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R11" }) }, 147 { ArmRegisters.R12, new CPURegister(12, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R12" }) }, 148 { ArmRegisters.SP, new CPURegister(13, 32, isGeneral: true, isReadonly: false, aliases: new [] { "SP", "R13" }) }, 149 { ArmRegisters.LR, new CPURegister(14, 32, isGeneral: true, isReadonly: false, aliases: new [] { "LR", "R14" }) }, 150 { ArmRegisters.PC, new CPURegister(15, 32, isGeneral: true, isReadonly: false, aliases: new [] { "PC", "R15" }) }, 151 { ArmRegisters.CPSR, new CPURegister(25, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CPSR" }) }, 152 }; 153 } 154 155 public enum ArmRegisters 156 { 157 SP = 13, 158 LR = 14, 159 PC = 15, 160 CPSR = 25, 161 R0 = 0, 162 R1 = 1, 163 R2 = 2, 164 R3 = 3, 165 R4 = 4, 166 R5 = 5, 167 R6 = 6, 168 R7 = 7, 169 R8 = 8, 170 R9 = 9, 171 R10 = 10, 172 R11 = 11, 173 R12 = 12, 174 R13 = 13, 175 R14 = 14, 176 R15 = 15, 177 } 178 } 179
