1 /********************************************************
2 *
3 * Warning!
4 * This file was generated automatically.
5 * Please do not edit. Changes should be made in the
6 * appropriate *.tt file.
7 *
8 */
9 using System;
10 using System.Linq;
11 using System.Collections.Generic;
12 using Antmicro.Renode.Peripherals.CPU.Registers;
13 using Antmicro.Renode.Utilities.Binding;
14 using Antmicro.Renode.Exceptions;
15 
16 namespace Antmicro.Renode.Peripherals.CPU
17 {
18     public partial class CortexM
19     {
SetRegister(int register, RegisterValue value)20         public override void SetRegister(int register, RegisterValue value)
21         {
22             if(!mapping.TryGetValue((CortexMRegisters)register, out var r))
23             {
24                 throw new RecoverableException($"Wrong register index: {register}");
25             }
26 
27             SetRegisterValue32(r.Index, checked((uint)value));
28         }
29 
GetRegister(int register)30         public override RegisterValue GetRegister(int register)
31         {
32             if(!mapping.TryGetValue((CortexMRegisters)register, out var r))
33             {
34                 throw new RecoverableException($"Wrong register index: {register}");
35             }
36             return GetRegisterValue32(r.Index);
37         }
38 
GetRegisters()39         public override IEnumerable<CPURegister> GetRegisters()
40         {
41             return mapping.Values.OrderBy(x => x.Index);
42         }
43 
44         [Register]
45         public RegisterValue Control
46         {
47             get
48             {
49                 return GetRegisterValue32((int)CortexMRegisters.Control);
50             }
51             set
52             {
53                 SetRegisterValue32((int)CortexMRegisters.Control, value);
54             }
55         }
56         [Register]
57         public RegisterValue BasePri
58         {
59             get
60             {
61                 return GetRegisterValue32((int)CortexMRegisters.BasePri);
62             }
63             set
64             {
65                 SetRegisterValue32((int)CortexMRegisters.BasePri, value);
66             }
67         }
68         [Register]
69         public RegisterValue VecBase
70         {
71             get
72             {
73                 return GetRegisterValue32((int)CortexMRegisters.VecBase);
74             }
75             set
76             {
77                 SetRegisterValue32((int)CortexMRegisters.VecBase, value);
78             }
79         }
80         [Register]
81         public RegisterValue CurrentSP
82         {
83             get
84             {
85                 return GetRegisterValue32((int)CortexMRegisters.CurrentSP);
86             }
87             set
88             {
89                 SetRegisterValue32((int)CortexMRegisters.CurrentSP, value);
90             }
91         }
92         [Register]
93         public RegisterValue OtherSP
94         {
95             get
96             {
97                 return GetRegisterValue32((int)CortexMRegisters.OtherSP);
98             }
99             set
100             {
101                 SetRegisterValue32((int)CortexMRegisters.OtherSP, value);
102             }
103         }
104         [Register]
105         public RegisterValue FPCCR
106         {
107             get
108             {
109                 return GetRegisterValue32((int)CortexMRegisters.FPCCR);
110             }
111             set
112             {
113                 SetRegisterValue32((int)CortexMRegisters.FPCCR, value);
114             }
115         }
116         [Register]
117         public RegisterValue FPCAR
118         {
119             get
120             {
121                 return GetRegisterValue32((int)CortexMRegisters.FPCAR);
122             }
123             set
124             {
125                 SetRegisterValue32((int)CortexMRegisters.FPCAR, value);
126             }
127         }
128         [Register]
129         public RegisterValue FPDSCR
130         {
131             get
132             {
133                 return GetRegisterValue32((int)CortexMRegisters.FPDSCR);
134             }
135             set
136             {
137                 SetRegisterValue32((int)CortexMRegisters.FPDSCR, value);
138             }
139         }
140         [Register]
141         public RegisterValue CPACR
142         {
143             get
144             {
145                 return GetRegisterValue32((int)CortexMRegisters.CPACR);
146             }
147             set
148             {
149                 SetRegisterValue32((int)CortexMRegisters.CPACR, value);
150             }
151         }
152         [Register]
153         public RegisterValue PRIMASK
154         {
155             get
156             {
157                 return GetRegisterValue32((int)CortexMRegisters.PRIMASK);
158             }
159             set
160             {
161                 SetRegisterValue32((int)CortexMRegisters.PRIMASK, value);
162             }
163         }
164         [Register]
165         public RegisterValue FAULTMASK
166         {
167             get
168             {
169                 return GetRegisterValue32((int)CortexMRegisters.FAULTMASK);
170             }
171             set
172             {
173                 SetRegisterValue32((int)CortexMRegisters.FAULTMASK, value);
174             }
175         }
176 
InitializeRegisters()177         protected override void InitializeRegisters()
178         {
179             base.InitializeRegisters();
180         }
181 
182         private static readonly Dictionary<CortexMRegisters, CPURegister> mapping = new Dictionary<CortexMRegisters, CPURegister>
183         {
184             { CortexMRegisters.R0,  new CPURegister(0, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R0" }) },
185             { CortexMRegisters.R1,  new CPURegister(1, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R1" }) },
186             { CortexMRegisters.R2,  new CPURegister(2, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R2" }) },
187             { CortexMRegisters.R3,  new CPURegister(3, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R3" }) },
188             { CortexMRegisters.R4,  new CPURegister(4, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R4" }) },
189             { CortexMRegisters.R5,  new CPURegister(5, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R5" }) },
190             { CortexMRegisters.R6,  new CPURegister(6, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R6" }) },
191             { CortexMRegisters.R7,  new CPURegister(7, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R7" }) },
192             { CortexMRegisters.R8,  new CPURegister(8, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R8" }) },
193             { CortexMRegisters.R9,  new CPURegister(9, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R9" }) },
194             { CortexMRegisters.R10,  new CPURegister(10, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R10" }) },
195             { CortexMRegisters.R11,  new CPURegister(11, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R11" }) },
196             { CortexMRegisters.R12,  new CPURegister(12, 32, isGeneral: true, isReadonly: false, aliases: new [] { "R12" }) },
197             { CortexMRegisters.SP,  new CPURegister(13, 32, isGeneral: true, isReadonly: false, aliases: new [] { "SP", "R13" }) },
198             { CortexMRegisters.LR,  new CPURegister(14, 32, isGeneral: true, isReadonly: false, aliases: new [] { "LR", "R14" }) },
199             { CortexMRegisters.PC,  new CPURegister(15, 32, isGeneral: true, isReadonly: false, aliases: new [] { "PC", "R15" }) },
200             { CortexMRegisters.Control,  new CPURegister(18, 32, isGeneral: false, isReadonly: false, aliases: new [] { "Control" }) },
201             { CortexMRegisters.BasePri,  new CPURegister(19, 32, isGeneral: false, isReadonly: false, aliases: new [] { "BasePri" }) },
202             { CortexMRegisters.VecBase,  new CPURegister(20, 32, isGeneral: false, isReadonly: false, aliases: new [] { "VecBase" }) },
203             { CortexMRegisters.CurrentSP,  new CPURegister(21, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CurrentSP" }) },
204             { CortexMRegisters.OtherSP,  new CPURegister(22, 32, isGeneral: false, isReadonly: false, aliases: new [] { "OtherSP" }) },
205             { CortexMRegisters.FPCCR,  new CPURegister(23, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FPCCR" }) },
206             { CortexMRegisters.FPCAR,  new CPURegister(24, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FPCAR" }) },
207             { CortexMRegisters.CPSR,  new CPURegister(25, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CPSR" }) },
208             { CortexMRegisters.FPDSCR,  new CPURegister(26, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FPDSCR" }) },
209             { CortexMRegisters.CPACR,  new CPURegister(27, 32, isGeneral: false, isReadonly: false, aliases: new [] { "CPACR" }) },
210             { CortexMRegisters.PRIMASK,  new CPURegister(28, 32, isGeneral: false, isReadonly: false, aliases: new [] { "PRIMASK" }) },
211             { CortexMRegisters.FAULTMASK,  new CPURegister(30, 32, isGeneral: false, isReadonly: false, aliases: new [] { "FAULTMASK" }) },
212         };
213     }
214 
215     public enum CortexMRegisters
216     {
217         SP = 13,
218         LR = 14,
219         PC = 15,
220         CPSR = 25,
221         Control = 18,
222         BasePri = 19,
223         VecBase = 20,
224         CurrentSP = 21,
225         OtherSP = 22,
226         FPCCR = 23,
227         FPCAR = 24,
228         FPDSCR = 26,
229         CPACR = 27,
230         PRIMASK = 28,
231         FAULTMASK = 30,
232         R0 = 0,
233         R1 = 1,
234         R2 = 2,
235         R3 = 3,
236         R4 = 4,
237         R5 = 5,
238         R6 = 6,
239         R7 = 7,
240         R8 = 8,
241         R9 = 9,
242         R10 = 10,
243         R11 = 11,
244         R12 = 12,
245         R13 = 13,
246         R14 = 14,
247         R15 = 15,
248     }
249 }
250