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Searched refs:CustomCSR (Results 1 – 4 of 4) sorted by relevance

/Renode-Infrastructure-v1.15.3-29f510e/src/Emulator/Cores/RiscV/
DVeeR_EL2.cs27 CreateCSRStub(CustomCSR.RegionAccessControl, "mrac"); in RegisterCustomCSRs()
28 CreateCSRStub(CustomCSR.CorePauseControl, "mcpc"); in RegisterCustomCSRs()
29 CreateCSRStub(CustomCSR.MemorySynchronizationTrigger, "dmst"); in RegisterCustomCSRs()
30 CreateCSRStub(CustomCSR.PowerManagementControl, "mpmc"); in RegisterCustomCSRs()
31 CreateCSRStub(CustomCSR.ICacheArrayWayIndexSelection, "dicawics"); in RegisterCustomCSRs()
32 CreateCSRStub(CustomCSR.ICacheArrayData0, "dicad0"); in RegisterCustomCSRs()
33 CreateCSRStub(CustomCSR.ICacheArrayData1, "dicad1"); in RegisterCustomCSRs()
34 CreateCSRStub(CustomCSR.ICacheArrayGo, "dicago"); in RegisterCustomCSRs()
35 CreateCSRStub(CustomCSR.ICacheDataArray0High, "dicac0h"); in RegisterCustomCSRs()
36 CreateCSRStub(CustomCSR.ForceDebugHaltThreshold, "mfdht"); in RegisterCustomCSRs()
[all …]
DAndes_AndeStarV5Extension.cs28 …cpu.RegisterCSR((ulong)CustomCSR.MachineMiscellaneousControl, () => machineMiscellaneousControlVal… in RegisterInternal()
35 …cpu.RegisterCSR((ulong)CustomCSR.MachineExtendedStatus, () => 0x0, value => { cpu.Log(LogLevel.War… in RegisterInternal()
36 …cpu.RegisterCSR((ulong)CustomCSR.MachineCacheControl, () => 0xffffffff, value => { cpu.Log(LogLeve… in RegisterInternal()
37 …cpu.RegisterCSR((ulong)CustomCSR.InstructionCacheAndMemoryConfiguration, () => 0x0, value => { cpu… in RegisterInternal()
38 …cpu.RegisterCSR((ulong)CustomCSR.DataCacheAndMemoryConfiguration, () => 0x0, value => { cpu.Log(Lo… in RegisterInternal()
39 …cpu.RegisterCSR((ulong)CustomCSR.MachineMiscellaneousConfiguration, () => 0x0, value => { cpu.Log(… in RegisterInternal()
40 …cpu.RegisterCSR((ulong)CustomCSR.MachineMiscellaneousConfigurationRV32, () => 0x0, value => { cpu.… in RegisterInternal()
41 …cpu.RegisterCSR((ulong)CustomCSR.VectorProcessorConfiguration, () => 0x0, value => { cpu.Log(LogLe… in RegisterInternal()
42 …cpu.RegisterCSR((ulong)CustomCSR.ClusterCacheControlBaseAddress, () => 0x0, value => { cpu.Log(Log… in RegisterInternal()
43 …cpu.RegisterCSR((ulong)CustomCSR.Architecture, () => 0x0, value => { cpu.Log(LogLevel.Warning, "Wr… in RegisterInternal()
[all …]
DCV32E40P.cs23 …RegisterCSR((ulong)CustomCSR.PerformanceCounterMode, () => LogUnhandledCSRRead("PerformanceCounter… in CV32E40P()
24 …RegisterCSR((ulong)CustomCSR.StackCheckEnable , () => LogUnhandledCSRRead("StackCheckEnable")… in CV32E40P()
25 …RegisterCSR((ulong)CustomCSR.StackBase , () => LogUnhandledCSRRead("StackBase") … in CV32E40P()
26 …RegisterCSR((ulong)CustomCSR.StackEnd , () => LogUnhandledCSRRead("StackEnd") … in CV32E40P()
27 …RegisterCSR((ulong)CustomCSR.HardwareLoop0Start , () => LogUnhandledCSRRead("HardwareLoop0Start… in CV32E40P()
28 …RegisterCSR((ulong)CustomCSR.HardwareLoop0End , () => LogUnhandledCSRRead("HardwareLoop0End")… in CV32E40P()
29 …RegisterCSR((ulong)CustomCSR.HardwareLoop0Counter , () => LogUnhandledCSRRead("HardwareLoop0Count… in CV32E40P()
30 …RegisterCSR((ulong)CustomCSR.HardwareLoop1Start , () => LogUnhandledCSRRead("HardwareLoop1Start… in CV32E40P()
31 …RegisterCSR((ulong)CustomCSR.HardwareLoop1End , () => LogUnhandledCSRRead("HardwareLoop1End")… in CV32E40P()
32 …RegisterCSR((ulong)CustomCSR.HardwareLoop1Counter , () => LogUnhandledCSRRead("HardwareLoop1Count… in CV32E40P()
[all …]
DOpenTitan_BigNumberAcceleratorCore.cs235 RegisterCSR((ulong)CustomCSR.FlagGroup0, in RegisterCustomCSRs()
240 RegisterCSR((ulong)CustomCSR.FlagGroup1, in RegisterCustomCSRs()
245 RegisterCSR((ulong)CustomCSR.Flags, in RegisterCustomCSRs()
253 RegisterCSR((ulong)(CustomCSR.Mod0 + index), in RegisterCustomCSRs()
259 RegisterCSR((ulong)CustomCSR.RndPrefetch, in RegisterCustomCSRs()
265 RegisterCSR((ulong)CustomCSR.Rnd, in RegisterCustomCSRs()
270 RegisterCSR((ulong)CustomCSR.URnd, in RegisterCustomCSRs()
968 private enum CustomCSR enum in Antmicro.Renode.Peripherals.CPU.OpenTitan_BigNumberAcceleratorCore