Lines Matching refs:Address
289 Write Opcode To Address ${pc} 0xDEADBEEF
303 Set Exception Vector Base Address
354 Write Opcode To Address
459 Add Dummy Memory At Hivecs Base Address
462 Check Protection Region Address Register Access Through Selector Register
471 Check Protection Region Address Register Access Through Direct Register
495 …Write Opcode To Address 0x8000 0xE3080010 # mov r0, #0x8010 @ HA…
496 …Write Opcode To Address 0x8004 0xEE8C0F10 # mcr p15, 4, r0, c12, …
497 Write Opcode To Address 0x8008 ${opcode} # instruction #0
498 Write Opcode To Address 0x800C 0xEAFFFFFD # b 0x8008
499 Write Opcode To Address 0x8010 0xE1A00000 # nop
500 Write Opcode To Address 0x8014 0xE1A00000 # nop
501 Write Opcode To Address 0x8018 0xE1A00000 # nop
502 Write Opcode To Address 0x801C 0xE160006E # eret
526 Set Exception Vector Base Address ${pl} ${EXCEPTION_HANDLER_BASE_ADDRESS}
542 Set Exception Vector Base Address ${pl} ${EXCEPTION_HANDLER_BASE_ADDRESS}
584 Write Opcode To Address 0x8000 0xe16ef300 # msr SPSR_hyp, r0
606 …Write Opcode To Address 0x8000 0xe30c0afe # movw r0, #51966 …
607 Write Opcode To Address 0x8004 0xe12ef300 # msr ELR_hyp, r0
608 Write Opcode To Address 0x8008 0xe10e1300 # mrs r1, ELR_hyp
609 Write Opcode To Address 0x800C 0xe1500001 # cmp r0, r1
630 Write Opcode To Address 0x8000 0xe321f010 # msr CPSR_c, #16
659 Set Exception Vector Base Address ${pl} ${EXCEPTION_VECTOR_ADDRESS}
675 …Add Dummy Memory At Hivecs Base Address # Prevent CPU abort error when trying to ex…
689 Check Protection Region Address Register Access Template
712 …Check Protection Region Address Register Access Through Selector Register ${direct_addr_reg} ${s…
713 …Check Protection Region Address Register Access Through Direct Register ${direct_addr_reg} ${sel…
870 ### Address Translation Registers
872 Check Protection Region Address Register Access
873 [Template] Check Protection Region Address Register Access Template